diff mbox series

opal entry: Fix LE skiboot clobbering r10 argument

Message ID 20200429074021.1678584-1-npiggin@gmail.com
State Accepted
Headers show
Series opal entry: Fix LE skiboot clobbering r10 argument | expand

Checks

Context Check Description
snowpatch_ozlabs/apply_patch success Successfully applied on branch master (0f1937ef40fca0c3212a9dff1010b832a24fb063)
snowpatch_ozlabs/snowpatch_job_snowpatch-skiboot success Test snowpatch/job/snowpatch-skiboot on branch master
snowpatch_ozlabs/snowpatch_job_snowpatch-skiboot-dco success Signed-off-by present

Commit Message

Nicholas Piggin April 29, 2020, 7:40 a.m. UTC 
Fortunately no OPAL calls seem to use 8 arguments yet.

Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
---
 asm/head.S          | 2 +-
 include/asm-utils.h | 9 +++++----
 2 files changed, 6 insertions(+), 5 deletions(-)

Comments

Oliver O'Halloran May 26, 2020, 7:05 a.m. UTC | #1 
On Wed, Apr 29, 2020 at 5:41 PM Nicholas Piggin <npiggin@gmail.com> wrote:
>
> Fortunately no OPAL calls seem to use 8 arguments yet.
>
> Signed-off-by: Nicholas Piggin <npiggin@gmail.com>

Thanks, merged as 6327e0c158308c8b93ab01ada93753cb1b4364bf
diff mbox series

Patch

diff --git a/asm/head.S b/asm/head.S
index 88b2bc12a..3b41815c6 100644
--- a/asm/head.S
+++ b/asm/head.S
@@ -837,7 +837,7 @@  enter_nap:
 	.balign	0x10
 .global opal_entry
 opal_entry:
-	OPAL_ENTRY_TO_SKIBOOT_ENDIAN
+	OPAL_ENTRY_TO_SKIBOOT_ENDIAN /* This clobbers r11, r12 */
 
 	/* Get our per CPU pointer in r12 to check for quiesce */
 	mfspr	%r12,SPR_PIR
diff --git a/include/asm-utils.h b/include/asm-utils.h
index 73416cd0b..18325a8b3 100644
--- a/include/asm-utils.h
+++ b/include/asm-utils.h
@@ -28,16 +28,17 @@ 
 /* Load an address via the TOC */
 #define LOAD_ADDR_FROM_TOC(r, e)	ld r,e@got(%r2)
 
-/* This must preserve LR, so can't use Linux kernel's FIXUP_ENDIAN */
+/* This must preserve LR, may only clobber r11-r12, so can't use Linux kernel's
+ * FIXUP_ENDIAN */
 #define SWITCH_ENDIAN						   \
 	.long 0xa600607d; /* mfmsr r11				*/ \
 	.long 0x01006b69; /* xori r11,r11,1			*/ \
 	.long 0xa64b7b7d; /* mthsrr1 r11			*/ \
 	.long 0xa602687d; /* mflr r11				*/ \
 	.long 0x05009f42; /* bcl 20,31,$+4			*/ \
-	.long 0xa602487d; /* mflr r10				*/ \
-	.long 0x14004a39; /* addi r10,r10,20			*/ \
-	.long 0xa64b5a7d; /* mthsrr0 r10			*/ \
+	.long 0xa602887d; /* mflr r12				*/ \
+	.long 0x14008c39; /* addi r12,r12,20			*/ \
+	.long 0xa64b9a7d; /* mthsrr0 r12			*/ \
 	.long 0xa603687d; /* mtlr r11				*/ \
 	.long 0x2402004c  /* hrfid				*/