From patchwork Fri Sep 20 13:58:22 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ryan Grimm X-Patchwork-Id: 1165218 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [203.11.71.2]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 46Zb6N4Zygz9s7T for ; Sat, 21 Sep 2019 00:03:40 +1000 (AEST) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=linux.ibm.com Received: from bilbo.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 46Zb6M6HSVzDrfJ for ; Sat, 21 Sep 2019 00:03:39 +1000 (AEST) X-Original-To: skiboot@lists.ozlabs.org Delivered-To: skiboot@lists.ozlabs.org Authentication-Results: lists.ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=linux.ibm.com (client-ip=148.163.156.1; helo=mx0a-001b2d01.pphosted.com; envelope-from=grimm@linux.ibm.com; receiver=) Authentication-Results: lists.ozlabs.org; dmarc=none (p=none dis=none) header.from=linux.ibm.com Received: from mx0a-001b2d01.pphosted.com (mx0a-001b2d01.pphosted.com [148.163.156.1]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 46Zb332DC2zDqWS for ; Sat, 21 Sep 2019 00:00:47 +1000 (AEST) Received: from pps.filterd (m0098396.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.16.0.27/8.16.0.27) with SMTP id x8KDqRgp045784 for ; Fri, 20 Sep 2019 10:00:44 -0400 Received: from ppma03dal.us.ibm.com (b.bd.3ea9.ip4.static.sl-reverse.com [169.62.189.11]) by mx0a-001b2d01.pphosted.com with ESMTP id 2v4wjd6fqb-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT) for ; Fri, 20 Sep 2019 10:00:43 -0400 Received: from pps.filterd (ppma03dal.us.ibm.com [127.0.0.1]) by ppma03dal.us.ibm.com (8.16.0.27/8.16.0.27) with SMTP id x8KDpJ1p021334 for ; Fri, 20 Sep 2019 14:00:42 GMT Received: from b03cxnp07029.gho.boulder.ibm.com (b03cxnp07029.gho.boulder.ibm.com [9.17.130.16]) by ppma03dal.us.ibm.com with ESMTP id 2v3vbuswwn-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT) for ; Fri, 20 Sep 2019 14:00:42 +0000 Received: from b03ledav002.gho.boulder.ibm.com (b03ledav002.gho.boulder.ibm.com [9.17.130.233]) by b03cxnp07029.gho.boulder.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id x8KE0dpg53870894 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Fri, 20 Sep 2019 14:00:39 GMT Received: from b03ledav002.gho.boulder.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id B992213605D; Fri, 20 Sep 2019 14:00:39 +0000 (GMT) Received: from b03ledav002.gho.boulder.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 803AF136067; Fri, 20 Sep 2019 14:00:38 +0000 (GMT) Received: from alain.ibm.com (unknown [9.85.201.128]) by b03ledav002.gho.boulder.ibm.com (Postfix) with ESMTP; Fri, 20 Sep 2019 14:00:38 +0000 (GMT) From: Ryan Grimm To: skiboot@lists.ozlabs.org Date: Fri, 20 Sep 2019 09:58:22 -0400 Message-Id: <20190920135823.471-8-grimm@linux.ibm.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190920135823.471-1-grimm@linux.ibm.com> References: <20190920135823.471-1-grimm@linux.ibm.com> MIME-Version: 1.0 X-TM-AS-GCONF: 00 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:, , definitions=2019-09-20_05:, , signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 malwarescore=0 suspectscore=1 phishscore=0 bulkscore=0 spamscore=0 clxscore=1015 lowpriorityscore=0 mlxscore=0 impostorscore=0 mlxlogscore=842 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1908290000 definitions=main-1909200135 Subject: [Skiboot] [RFC PATCH v2 7/8] occ: Disable OCC on UV systems X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: janani@us.ibm.com, "Gautham R . Shenoy" , suka@us.ibm.com, Ryan Grimm Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" On Ultravisor enabled system, temporarily disable OCC irq paths for shared memory updates when OCC is up, so as to boot the system. We also disable the OPAL-OCC command response interface which is required for Sensors. This will be enabled at a later point when we can read the OCC Common area residing in secure memory region. Disable stop levels if they are enabled in the SPIRA. Skip pstates_init and occ_sensor_init as well. Signed-off-by: Shilpasri G Bhat Signed-off-by: Gautham R. Shenoy Signed-off-by: Ryan Grimm --- hdata/spira.c | 4 ++++ hw/occ-sensor.c | 6 ++++++ hw/occ.c | 25 ++++++++++++++++++++++++- 3 files changed, 34 insertions(+), 1 deletion(-) diff --git a/hdata/spira.c b/hdata/spira.c index f6003ea0..5c65b139 100644 --- a/hdata/spira.c +++ b/hdata/spira.c @@ -1281,6 +1281,10 @@ static void add_stop_levels(void) if (proc_gen < proc_gen_p9) return; + if (is_msr_bit_set(MSR_S)) { + prlog(PR_INFO, "SPIRA: Skipping stop levels because S BIT set\n"); + } + /* * OPAL only exports a single set of flags to indicate the supported * STOP modes while the HDAT descibes the support top levels *per chip* diff --git a/hw/occ-sensor.c b/hw/occ-sensor.c index d06ca725..a0f47610 100644 --- a/hw/occ-sensor.c +++ b/hw/occ-sensor.c @@ -12,6 +12,7 @@ #include #include #include +#include enum sensor_attr { SENSOR_SAMPLE, @@ -492,6 +493,11 @@ bool occ_sensors_init(void) int occ_num = 0, i; bool has_gpu = false; + if (is_uv_present()) { + prlog(PR_DEBUG, "UV HACK: Skipping %s because MSR_S set\n", __func__); + return false; + } + /* OCC inband sensors is only supported in P9 */ if (proc_gen != proc_gen_p9) return false; diff --git a/hw/occ.c b/hw/occ.c index db2744ff..35582c89 100644 --- a/hw/occ.c +++ b/hw/occ.c @@ -872,6 +872,11 @@ static void occ_throttle_poll(void *data __unused) struct opal_occ_msg occ_msg; int rc; + if (is_uv_present()) { + prlog(PR_DEBUG, "OCC: %s currently unsupported on ultravisor\n", __func__); + return; + } + if (!try_lock(&occ_lock)) return; if (occ_reset) { @@ -1185,6 +1190,11 @@ static void handle_occ_rsp(uint32_t chip_id) struct opal_command_buffer *cmd; struct occ_response_buffer *rsp; + if (is_uv_present()) { + prlog(PR_DEBUG, "OCC: %s currently unsupported on ultravisor\n", __func__); + return; + } + chip = get_chip_cmd_interface(chip_id); if (!chip) return; @@ -1719,6 +1729,11 @@ void occ_pstates_init(void) u8 domain_runs_at; static bool occ_pstates_initialized; + if (is_msr_bit_set(MSR_S)) { + prlog(PR_DEBUG, "UV HACK: Skipping %s because UV is present\n", __func__); + return; + } + /* OCC is supported in P8 and P9 */ if (proc_gen < proc_gen_p8) return; @@ -1810,9 +1825,17 @@ void occ_pstates_init(void) /* Add opal_poller to poll OCC throttle status of each chip */ for_each_chip(chip) chip->throttle = 0; - opal_add_poller(occ_throttle_poll, NULL); occ_pstates_initialized = true; + /* + * On Ultravisor systems, we don't yet support + * OCC Poller and OPAL-OCC command-response interface. + */ + if (is_uv_present()) { + prlog(PR_DEBUG, "OCC: Skipping throttle-poll,CMD-RSP interface on UV\n"); + return; + } + opal_add_poller(occ_throttle_poll, NULL); /* Init OPAL-OCC command-response interface */ occ_cmd_interface_init();