diff mbox series

[RFC,v2,7/8] occ: Disable OCC on UV systems

Message ID 20190920135823.471-8-grimm@linux.ibm.com
State RFC
Headers show
Series PEF support in skiboot | expand

Checks

Context Check Description
snowpatch_ozlabs/apply_patch warning Failed to apply on branch master (470ffb5f29d741c3bed600f7bb7bf0cbb270e05a)
snowpatch_ozlabs/apply_patch fail Failed to apply to any branch

Commit Message

Ryan Grimm Sept. 20, 2019, 1:58 p.m. UTC 
On Ultravisor enabled system, temporarily disable OCC irq paths for
shared memory updates when OCC is up, so as to boot the system.

We also disable the OPAL-OCC command response interface which is
required for Sensors. This will be enabled at a later point when we
can read the OCC Common area residing in secure memory region.

Disable stop levels if they are enabled in the SPIRA.

Skip pstates_init and occ_sensor_init as well.

Signed-off-by: Shilpasri G Bhat <shilpa.bhat@linux.vnet.ibm.com>
Signed-off-by: Gautham R. Shenoy <ego@linux.vnet.ibm.com>
Signed-off-by: Ryan Grimm <grimm@linux.ibm.com>
---
 hdata/spira.c   |  4 ++++
 hw/occ-sensor.c |  6 ++++++
 hw/occ.c        | 25 ++++++++++++++++++++++++-
 3 files changed, 34 insertions(+), 1 deletion(-)

Comments

Oliver O'Halloran Nov. 17, 2019, 11:58 p.m. UTC | #1 
On Sat, Sep 21, 2019 at 12:04 AM Ryan Grimm <grimm@linux.ibm.com> wrote:
>
> On Ultravisor enabled system, temporarily disable OCC irq paths for
> shared memory updates when OCC is up, so as to boot the system.
>
> We also disable the OPAL-OCC command response interface which is
> required for Sensors. This will be enabled at a later point when we
> can read the OCC Common area residing in secure memory region.
>
> Disable stop levels if they are enabled in the SPIRA.
>
> Skip pstates_init and occ_sensor_init as well.
>
> Signed-off-by: Shilpasri G Bhat <shilpa.bhat@linux.vnet.ibm.com>
> Signed-off-by: Gautham R. Shenoy <ego@linux.vnet.ibm.com>
> Signed-off-by: Ryan Grimm <grimm@linux.ibm.com>

Is there any OCC functions that are still enabled? If not, I'd be
happier if we just had a way to disable the OCC entirely rather than
doing S bits checks and playing wack-a-mole.

> ---
>  hdata/spira.c   |  4 ++++
>  hw/occ-sensor.c |  6 ++++++
>  hw/occ.c        | 25 ++++++++++++++++++++++++-
>  3 files changed, 34 insertions(+), 1 deletion(-)
>
> diff --git a/hdata/spira.c b/hdata/spira.c
> index f6003ea0..5c65b139 100644
> --- a/hdata/spira.c
> +++ b/hdata/spira.c
> @@ -1281,6 +1281,10 @@ static void add_stop_levels(void)
>         if (proc_gen < proc_gen_p9)
>                 return;
>
> +       if (is_msr_bit_set(MSR_S)) {
> +               prlog(PR_INFO, "SPIRA: Skipping stop levels because S BIT set\n");
> +       }
> +
>         /*
>          * OPAL only exports a single set of flags to indicate the supported
>          * STOP modes while the HDAT descibes the support top levels *per chip*
> diff --git a/hw/occ-sensor.c b/hw/occ-sensor.c
> index d06ca725..a0f47610 100644
> --- a/hw/occ-sensor.c
> +++ b/hw/occ-sensor.c
> @@ -12,6 +12,7 @@
>  #include <device.h>
>  #include <cpu.h>
>  #include <occ.h>
> +#include <ultravisor.h>
>
>  enum sensor_attr {
>         SENSOR_SAMPLE,
> @@ -492,6 +493,11 @@ bool occ_sensors_init(void)
>         int occ_num = 0, i;
>         bool has_gpu = false;
>
> +       if (is_uv_present()) {
> +               prlog(PR_DEBUG, "UV HACK: Skipping %s because MSR_S set\n", __func__);
> +               return false;
> +       }
> +
>         /* OCC inband sensors is only supported in P9 */
>         if (proc_gen != proc_gen_p9)
>                 return false;
> diff --git a/hw/occ.c b/hw/occ.c
> index db2744ff..35582c89 100644
> --- a/hw/occ.c
> +++ b/hw/occ.c
> @@ -872,6 +872,11 @@ static void occ_throttle_poll(void *data __unused)
>         struct opal_occ_msg occ_msg;
>         int rc;
>
> +       if (is_uv_present()) {
> +               prlog(PR_DEBUG, "OCC: %s currently unsupported on ultravisor\n", __func__);
> +               return;
> +       }
> +
>         if (!try_lock(&occ_lock))
>                 return;
>         if (occ_reset) {
> @@ -1185,6 +1190,11 @@ static void handle_occ_rsp(uint32_t chip_id)
>         struct opal_command_buffer *cmd;
>         struct occ_response_buffer *rsp;
>
> +       if (is_uv_present()) {
> +               prlog(PR_DEBUG, "OCC: %s currently unsupported on ultravisor\n", __func__);
> +               return;
> +       }
> +
>         chip = get_chip_cmd_interface(chip_id);
>         if (!chip)
>                 return;
> @@ -1719,6 +1729,11 @@ void occ_pstates_init(void)
>         u8 domain_runs_at;
>         static bool occ_pstates_initialized;
>
> +       if (is_msr_bit_set(MSR_S)) {
> +               prlog(PR_DEBUG, "UV HACK: Skipping %s because UV is present\n", __func__);
> +               return;
> +       }
> +
>         /* OCC is supported in P8 and P9 */
>         if (proc_gen < proc_gen_p8)
>                 return;
> @@ -1810,9 +1825,17 @@ void occ_pstates_init(void)
>         /* Add opal_poller to poll OCC throttle status of each chip */
>         for_each_chip(chip)
>                 chip->throttle = 0;
> -       opal_add_poller(occ_throttle_poll, NULL);
>         occ_pstates_initialized = true;
>
> +       /*
> +        * On Ultravisor systems, we don't yet support
> +        * OCC Poller and OPAL-OCC command-response interface.
> +        */
> +       if (is_uv_present()) {
> +               prlog(PR_DEBUG, "OCC: Skipping throttle-poll,CMD-RSP interface on UV\n");
> +               return;
> +       }
> +       opal_add_poller(occ_throttle_poll, NULL);
>         /* Init OPAL-OCC command-response interface */
>         occ_cmd_interface_init();
>
> --
> 2.21.0
>
> _______________________________________________
> Skiboot mailing list
> Skiboot@lists.ozlabs.org
> https://lists.ozlabs.org/listinfo/skiboot
diff mbox series

Patch

diff --git a/hdata/spira.c b/hdata/spira.c
index f6003ea0..5c65b139 100644
--- a/hdata/spira.c
+++ b/hdata/spira.c
@@ -1281,6 +1281,10 @@  static void add_stop_levels(void)
 	if (proc_gen < proc_gen_p9)
 		return;
 
+	if (is_msr_bit_set(MSR_S)) {
+		prlog(PR_INFO, "SPIRA: Skipping stop levels because S BIT set\n");
+	}
+
 	/*
 	 * OPAL only exports a single set of flags to indicate the supported
 	 * STOP modes while the HDAT descibes the support top levels *per chip*
diff --git a/hw/occ-sensor.c b/hw/occ-sensor.c
index d06ca725..a0f47610 100644
--- a/hw/occ-sensor.c
+++ b/hw/occ-sensor.c
@@ -12,6 +12,7 @@ 
 #include <device.h>
 #include <cpu.h>
 #include <occ.h>
+#include <ultravisor.h>
 
 enum sensor_attr {
 	SENSOR_SAMPLE,
@@ -492,6 +493,11 @@  bool occ_sensors_init(void)
 	int occ_num = 0, i;
 	bool has_gpu = false;
 
+	if (is_uv_present()) {
+		prlog(PR_DEBUG, "UV HACK: Skipping %s because MSR_S set\n", __func__);
+		return false;
+	}
+
 	/* OCC inband sensors is only supported in P9 */
 	if (proc_gen != proc_gen_p9)
 		return false;
diff --git a/hw/occ.c b/hw/occ.c
index db2744ff..35582c89 100644
--- a/hw/occ.c
+++ b/hw/occ.c
@@ -872,6 +872,11 @@  static void occ_throttle_poll(void *data __unused)
 	struct opal_occ_msg occ_msg;
 	int rc;
 
+	if (is_uv_present()) {
+		prlog(PR_DEBUG, "OCC: %s currently unsupported on ultravisor\n", __func__);
+		return;
+	}
+
 	if (!try_lock(&occ_lock))
 		return;
 	if (occ_reset) {
@@ -1185,6 +1190,11 @@  static void handle_occ_rsp(uint32_t chip_id)
 	struct opal_command_buffer *cmd;
 	struct occ_response_buffer *rsp;
 
+	if (is_uv_present()) {
+		prlog(PR_DEBUG, "OCC: %s currently unsupported on ultravisor\n", __func__);
+		return;
+	}
+
 	chip = get_chip_cmd_interface(chip_id);
 	if (!chip)
 		return;
@@ -1719,6 +1729,11 @@  void occ_pstates_init(void)
 	u8 domain_runs_at;
 	static bool occ_pstates_initialized;
 
+	if (is_msr_bit_set(MSR_S)) {
+		prlog(PR_DEBUG, "UV HACK: Skipping %s because UV is present\n", __func__);
+		return;
+	}
+
 	/* OCC is supported in P8 and P9 */
 	if (proc_gen < proc_gen_p8)
 		return;
@@ -1810,9 +1825,17 @@  void occ_pstates_init(void)
 	/* Add opal_poller to poll OCC throttle status of each chip */
 	for_each_chip(chip)
 		chip->throttle = 0;
-	opal_add_poller(occ_throttle_poll, NULL);
 	occ_pstates_initialized = true;
 
+	/*
+	 * On Ultravisor systems, we don't yet support
+	 * OCC Poller and OPAL-OCC command-response interface.
+	 */
+	if (is_uv_present()) {
+		prlog(PR_DEBUG, "OCC: Skipping throttle-poll,CMD-RSP interface on UV\n");
+		return;
+	}
+	opal_add_poller(occ_throttle_poll, NULL);
 	/* Init OPAL-OCC command-response interface */
 	occ_cmd_interface_init();