| Message ID | 20190909123151.21944-9-fbarrat@linux.ibm.com |
|---|---|
| State | Superseded |
| Headers | show |
| Series | opencapi: enable card reset and link retraining | expand |
| Context | Check | Description |
|---|---|---|
| snowpatch_ozlabs/apply_patch | success | Successfully applied on branch master (470ffb5f29d741c3bed600f7bb7bf0cbb270e05a) |
| snowpatch_ozlabs/snowpatch_job_snowpatch-skiboot | success | Test snowpatch/job/snowpatch-skiboot on branch master |
| snowpatch_ozlabs/snowpatch_job_snowpatch-skiboot-dco | success | Signed-off-by present |
On 09/09/2019 14:31, Frederic Barrat wrote: > Link retraining was showing reliability problems due to some > opencapi-only settings not being optimized. This patch updates some > extra PHY state, as agreed with the PHY team. Though they mostly > impact link retraining behavior, they should also be set at boot. > > Signed-off-by: Frederic Barrat <fbarrat@linux.ibm.com> > --- Reviewed-by: Christophe Lombard <clombard@linux.vnet.ibm.com>
On 9/9/19 2:31 pm, Frederic Barrat wrote: > Link retraining was showing reliability problems due to some > opencapi-only settings not being optimized. This patch updates some > extra PHY state, as agreed with the PHY team. Though they mostly > impact link retraining behavior, they should also be set at boot. > > Signed-off-by: Frederic Barrat <fbarrat@linux.ibm.com> I'm not a PHY expert so can't comment on the magic values, but otherwise this code looks fine. Reviewed-by: Andrew Donnellan <ajd@linux.ibm.com> > --- > hw/npu2-hw-procedures.c | 16 ++++++++++++++++ > 1 file changed, 16 insertions(+) > > diff --git a/hw/npu2-hw-procedures.c b/hw/npu2-hw-procedures.c > index 6cd780cc..ad1627ae 100644 > --- a/hw/npu2-hw-procedures.c > +++ b/hw/npu2-hw-procedures.c > @@ -60,8 +60,14 @@ static struct npu2_phy_reg NPU2_PHY_RX_PR_FW_OFF = {0x08a, 56, 1}; > static struct npu2_phy_reg NPU2_PHY_RX_PR_FW_INERTIA_AMT = {0x08a, 57, 3}; > static struct npu2_phy_reg NPU2_PHY_RX_CFG_LTE_MC = {0x000, 60, 4}; > static struct npu2_phy_reg NPU2_PHY_RX_A_INTEG_COARSE_GAIN = {0x00a, 48, 4}; > +static struct npu2_phy_reg NPU2_PHY_RX_A_CTLE_COARSE = {0x00c, 48, 5}; > +static struct npu2_phy_reg NPU2_PHY_RX_A_CTLE_GAIN = {0x00c, 53, 4}; > static struct npu2_phy_reg NPU2_PHY_RX_B_INTEG_COARSE_GAIN = {0x026, 48, 4}; > +static struct npu2_phy_reg NPU2_PHY_RX_B_CTLE_COARSE = {0x028, 48, 5}; > +static struct npu2_phy_reg NPU2_PHY_RX_B_CTLE_GAIN = {0x028, 53, 4}; > static struct npu2_phy_reg NPU2_PHY_RX_E_INTEG_COARSE_GAIN = {0x030, 48, 4}; > +static struct npu2_phy_reg NPU2_PHY_RX_E_CTLE_COARSE = {0x032, 48, 5}; > +static struct npu2_phy_reg NPU2_PHY_RX_E_CTLE_GAIN = {0x032, 53, 4}; > > /* These registers are per-PHY, not per lane */ > static struct npu2_phy_reg NPU2_PHY_RX_SPEED_SELECT = {0x262, 51, 2}; > @@ -429,6 +435,16 @@ static uint32_t phy_reset_complete(struct npu2_dev *ndev) > phy_write_lane(ndev, &NPU2_PHY_RX_A_INTEG_COARSE_GAIN, lane, 11); > phy_write_lane(ndev, &NPU2_PHY_RX_B_INTEG_COARSE_GAIN, lane, 11); > phy_write_lane(ndev, &NPU2_PHY_RX_E_INTEG_COARSE_GAIN, lane, 11); > + > + if (ndev->type == NPU2_DEV_TYPE_OPENCAPI) { > + phy_write_lane(ndev, &NPU2_PHY_RX_A_CTLE_GAIN, lane, 0); > + phy_write_lane(ndev, &NPU2_PHY_RX_B_CTLE_GAIN, lane, 0); > + phy_write_lane(ndev, &NPU2_PHY_RX_E_CTLE_GAIN, lane, 0); > + > + phy_write_lane(ndev, &NPU2_PHY_RX_A_CTLE_COARSE, lane, 20); > + phy_write_lane(ndev, &NPU2_PHY_RX_B_CTLE_COARSE, lane, 20); > + phy_write_lane(ndev, &NPU2_PHY_RX_E_CTLE_COARSE, lane, 20); > + } > } > > set_iovalid(ndev, true); >
diff --git a/hw/npu2-hw-procedures.c b/hw/npu2-hw-procedures.c index 6cd780cc..ad1627ae 100644 --- a/hw/npu2-hw-procedures.c +++ b/hw/npu2-hw-procedures.c @@ -60,8 +60,14 @@ static struct npu2_phy_reg NPU2_PHY_RX_PR_FW_OFF = {0x08a, 56, 1}; static struct npu2_phy_reg NPU2_PHY_RX_PR_FW_INERTIA_AMT = {0x08a, 57, 3}; static struct npu2_phy_reg NPU2_PHY_RX_CFG_LTE_MC = {0x000, 60, 4}; static struct npu2_phy_reg NPU2_PHY_RX_A_INTEG_COARSE_GAIN = {0x00a, 48, 4}; +static struct npu2_phy_reg NPU2_PHY_RX_A_CTLE_COARSE = {0x00c, 48, 5}; +static struct npu2_phy_reg NPU2_PHY_RX_A_CTLE_GAIN = {0x00c, 53, 4}; static struct npu2_phy_reg NPU2_PHY_RX_B_INTEG_COARSE_GAIN = {0x026, 48, 4}; +static struct npu2_phy_reg NPU2_PHY_RX_B_CTLE_COARSE = {0x028, 48, 5}; +static struct npu2_phy_reg NPU2_PHY_RX_B_CTLE_GAIN = {0x028, 53, 4}; static struct npu2_phy_reg NPU2_PHY_RX_E_INTEG_COARSE_GAIN = {0x030, 48, 4}; +static struct npu2_phy_reg NPU2_PHY_RX_E_CTLE_COARSE = {0x032, 48, 5}; +static struct npu2_phy_reg NPU2_PHY_RX_E_CTLE_GAIN = {0x032, 53, 4}; /* These registers are per-PHY, not per lane */ static struct npu2_phy_reg NPU2_PHY_RX_SPEED_SELECT = {0x262, 51, 2}; @@ -429,6 +435,16 @@ static uint32_t phy_reset_complete(struct npu2_dev *ndev) phy_write_lane(ndev, &NPU2_PHY_RX_A_INTEG_COARSE_GAIN, lane, 11); phy_write_lane(ndev, &NPU2_PHY_RX_B_INTEG_COARSE_GAIN, lane, 11); phy_write_lane(ndev, &NPU2_PHY_RX_E_INTEG_COARSE_GAIN, lane, 11); + + if (ndev->type == NPU2_DEV_TYPE_OPENCAPI) { + phy_write_lane(ndev, &NPU2_PHY_RX_A_CTLE_GAIN, lane, 0); + phy_write_lane(ndev, &NPU2_PHY_RX_B_CTLE_GAIN, lane, 0); + phy_write_lane(ndev, &NPU2_PHY_RX_E_CTLE_GAIN, lane, 0); + + phy_write_lane(ndev, &NPU2_PHY_RX_A_CTLE_COARSE, lane, 20); + phy_write_lane(ndev, &NPU2_PHY_RX_B_CTLE_COARSE, lane, 20); + phy_write_lane(ndev, &NPU2_PHY_RX_E_CTLE_COARSE, lane, 20); + } } set_iovalid(ndev, true);
Link retraining was showing reliability problems due to some opencapi-only settings not being optimized. This patch updates some extra PHY state, as agreed with the PHY team. Though they mostly impact link retraining behavior, they should also be set at boot. Signed-off-by: Frederic Barrat <fbarrat@linux.ibm.com> --- hw/npu2-hw-procedures.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+)