From patchwork Tue Jun 18 07:29:23 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stewart Smith X-Patchwork-Id: 1117664 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 45SfvR60f4z9s5c for ; Tue, 18 Jun 2019 17:33:23 +1000 (AEST) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=linux.ibm.com Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 45SfvR3sqhzDqgN for ; Tue, 18 Jun 2019 17:33:23 +1000 (AEST) X-Original-To: skiboot@lists.ozlabs.org Delivered-To: skiboot@lists.ozlabs.org Authentication-Results: lists.ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=linux.ibm.com (client-ip=148.163.156.1; helo=mx0a-001b2d01.pphosted.com; envelope-from=stewart@linux.ibm.com; receiver=) Authentication-Results: lists.ozlabs.org; dmarc=none (p=none dis=none) header.from=linux.ibm.com Received: from mx0a-001b2d01.pphosted.com (mx0a-001b2d01.pphosted.com [148.163.156.1]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 45Sfq74yBMzDqYb for ; Tue, 18 Jun 2019 17:29:39 +1000 (AEST) Received: from pps.filterd (m0098396.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.16.0.27/8.16.0.27) with SMTP id x5I7SWIm052908 for ; Tue, 18 Jun 2019 03:29:38 -0400 Received: from e32.co.us.ibm.com (e32.co.us.ibm.com [32.97.110.150]) by mx0a-001b2d01.pphosted.com with ESMTP id 2t6rmte5ht-1 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=NOT) for ; Tue, 18 Jun 2019 03:29:37 -0400 Received: from localhost by e32.co.us.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! 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Violators will be prosecuted; (version=TLSv1/SSLv3 cipher=AES256-GCM-SHA384 bits=256/256) Tue, 18 Jun 2019 08:29:34 +0100 Received: from b03ledav003.gho.boulder.ibm.com (b03ledav003.gho.boulder.ibm.com [9.17.130.234]) by b03cxnp07028.gho.boulder.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id x5I7TXla24838642 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK) for ; Tue, 18 Jun 2019 07:29:34 GMT Received: from b03ledav003.gho.boulder.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id D1A646A05A for ; Tue, 18 Jun 2019 07:29:33 +0000 (GMT) Received: from b03ledav003.gho.boulder.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 6E1AB6A04D for ; Tue, 18 Jun 2019 07:29:33 +0000 (GMT) Received: from birb.localdomain (unknown [9.185.142.124]) by b03ledav003.gho.boulder.ibm.com (Postfix) with ESMTP for ; Tue, 18 Jun 2019 07:29:33 +0000 (GMT) Received: by birb.localdomain (Postfix, from userid 1000) id 815B54C4BC7; Tue, 18 Jun 2019 17:29:28 +1000 (AEST) From: Stewart Smith To: skiboot@lists.ozlabs.org Date: Tue, 18 Jun 2019 17:29:23 +1000 X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190618072925.5299-1-stewart@linux.ibm.com> References: <20190618072925.5299-1-stewart@linux.ibm.com> MIME-Version: 1.0 X-TM-AS-GCONF: 00 x-cbid: 19061807-0004-0000-0000-0000151DAC58 X-IBM-SpamModules-Scores: X-IBM-SpamModules-Versions: BY=3.00011283; HX=3.00000242; KW=3.00000007; PH=3.00000004; SC=3.00000286; SDB=6.01219633; UDB=6.00641533; IPR=6.01000774; MB=3.00027356; MTD=3.00000008; XFM=3.00000015; UTC=2019-06-18 07:29:35 X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 19061807-0005-0000-0000-00008C200E5B Message-Id: <20190618072925.5299-16-stewart@linux.ibm.com> X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:, , definitions=2019-06-18_04:, , signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 malwarescore=0 suspectscore=1 phishscore=0 bulkscore=0 spamscore=0 clxscore=1015 lowpriorityscore=0 mlxscore=0 impostorscore=0 mlxlogscore=999 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1810050000 definitions=main-1906180062 Subject: [Skiboot] [PATCH 15/17] Separate FSP specific PSI code X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" Signed-off-by: Stewart Smith --- hw/fsp/Makefile.inc | 2 +- hw/fsp/fsp-psi.c | 97 +++++++++++++++++++++++++++++++++++++ hw/psi.c | 94 ++++------------------------------- include/platform.h | 15 ++++++ include/psi.h | 2 +- platforms/ibm-fsp/common.c | 14 ++++++ platforms/ibm-fsp/firenze.c | 1 + platforms/ibm-fsp/ibm-fsp.h | 1 + platforms/ibm-fsp/zz.c | 1 + 9 files changed, 140 insertions(+), 87 deletions(-) create mode 100644 hw/fsp/fsp-psi.c diff --git a/hw/fsp/Makefile.inc b/hw/fsp/Makefile.inc index 4649621ca633..bcb3f3b95528 100644 --- a/hw/fsp/Makefile.inc +++ b/hw/fsp/Makefile.inc @@ -5,6 +5,6 @@ FSP_OBJS += fsp-surveillance.o fsp-codeupdate.o fsp-sensor.o FSP_OBJS += fsp-diag.o fsp-leds.o fsp-mem-err.o fsp-op-panel.o FSP_OBJS += fsp-elog-read.o fsp-elog-write.o fsp-epow.o fsp-dpo.o FSP_OBJS += fsp-dump.o fsp-mdst-table.o fsp-chiptod.o fsp-ipmi.o -FSP_OBJS += fsp-attn.o fsp-occ.o +FSP_OBJS += fsp-attn.o fsp-occ.o fsp-psi.o FSP = hw/fsp/built-in.a $(FSP): $(FSP_OBJS:%=hw/fsp/%) diff --git a/hw/fsp/fsp-psi.c b/hw/fsp/fsp-psi.c new file mode 100644 index 000000000000..6c2d4bf70a5a --- /dev/null +++ b/hw/fsp/fsp-psi.c @@ -0,0 +1,97 @@ +/* Copyright 2013-2014 IBM Corp. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + * implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include +#include +#include +#include + +static void psi_tce_enable(struct psi *psi, bool enable) +{ + void *addr; + u64 val; + + switch (proc_gen) { + case proc_gen_p8: + case proc_gen_p9: + addr = psi->regs + PSIHB_PHBSCR; + break; + default: + prerror("%s: Unknown CPU type\n", __func__); + return; + } + + val = in_be64(addr); + if (enable) + val |= PSIHB_CR_TCE_ENABLE; + else + val &= ~PSIHB_CR_TCE_ENABLE; + out_be64(addr, val); +} + +/* + * Configure the PSI interface for communicating with + * an FSP, such as enabling the TCEs, FSP commands, + * etc... + */ +void psi_init_for_fsp(struct psi *psi) +{ + uint64_t reg; + bool enable_tce = true; + + lock(&psi_lock); + + /* Disable and setup TCE base address */ + psi_tce_enable(psi, false); + + switch (proc_gen) { + case proc_gen_p8: + case proc_gen_p9: + out_be64(psi->regs + PSIHB_TAR, PSI_TCE_TABLE_BASE | + PSIHB_TAR_256K_ENTRIES); + break; + default: + enable_tce = false; + }; + + /* Enable various other configuration register bits based + * on what pHyp does. We keep interrupts disabled until + * after the mailbox has been properly configured. We assume + * basic stuff such as PSI link enable is already there. + * + * - FSP CMD Enable + * - FSP MMIO Enable + * - TCE Enable + * - Error response enable + * + * Clear all other error bits + */ + if (!psi->active) { + prerror("PSI: psi_init_for_fsp() called on inactive link!\n"); + unlock(&psi_lock); + return; + } + + reg = in_be64(psi->regs + PSIHB_CR); + reg |= PSIHB_CR_FSP_CMD_ENABLE; + reg |= PSIHB_CR_FSP_MMIO_ENABLE; + reg |= PSIHB_CR_FSP_ERR_RSP_ENABLE; + reg &= ~0x00000000ffffffffull; + out_be64(psi->regs + PSIHB_CR, reg); + psi_tce_enable(psi, enable_tce); + + unlock(&psi_lock); +} diff --git a/hw/psi.c b/hw/psi.c index 5435c4655c2b..3b6ade1858d1 100644 --- a/hw/psi.c +++ b/hw/psi.c @@ -45,7 +45,7 @@ static bool psi_ext_irq_policy = EXTERNAL_IRQ_POLICY_LINUX; static void psi_activate_phb(struct psi *psi); -static struct lock psi_lock = LOCK_UNLOCKED; +struct lock psi_lock = LOCK_UNLOCKED; DEFINE_LOG_ENTRY(OPAL_RC_PSI_TIMEOUT, OPAL_PLATFORM_ERR_EVT, OPAL_PSI, OPAL_PLATFORM_FIRMWARE, @@ -199,7 +199,8 @@ static void psi_link_poll(void *data __unused) psi_activate_phb(psi); psi_set_link_polling(false); unlock(&psi_lock); - fsp_reinit_fsp(); + if (platform.psi && platform.psi->link_established) + platform.psi->link_established(); return; } } @@ -333,14 +334,14 @@ static void psihb_interrupt(struct irq_source *is, uint32_t isn __unused) */ if (!psi->active) psi_spurious_fsp_irq(psi); - else - fsp_interrupt(); + else { + if (platform.psi && platform.psi->fsp_interrupt) + platform.psi->fsp_interrupt(); + } } - /* Poll the console buffers on any interrupt since we don't - * get send notifications - */ - fsp_console_poll(NULL); + if (platform.psi && platform.psi->psihb_interrupt) + platform.psi->psihb_interrupt(); } @@ -627,83 +628,6 @@ static const struct irq_source_ops psi_p9_irq_ops = { .name = psi_p9_irq_name, }; -static void psi_tce_enable(struct psi *psi, bool enable) -{ - void *addr; - u64 val; - - switch (proc_gen) { - case proc_gen_p8: - case proc_gen_p9: - addr = psi->regs + PSIHB_PHBSCR; - break; - default: - prerror("%s: Unknown CPU type\n", __func__); - return; - } - - val = in_be64(addr); - if (enable) - val |= PSIHB_CR_TCE_ENABLE; - else - val &= ~PSIHB_CR_TCE_ENABLE; - out_be64(addr, val); -} - -/* - * Configure the PSI interface for communicating with - * an FSP, such as enabling the TCEs, FSP commands, - * etc... - */ -void psi_init_for_fsp(struct psi *psi) -{ - uint64_t reg; - bool enable_tce = true; - - lock(&psi_lock); - - /* Disable and setup TCE base address */ - psi_tce_enable(psi, false); - - switch (proc_gen) { - case proc_gen_p8: - case proc_gen_p9: - out_be64(psi->regs + PSIHB_TAR, PSI_TCE_TABLE_BASE | - PSIHB_TAR_256K_ENTRIES); - break; - default: - enable_tce = false; - }; - - /* Enable various other configuration register bits based - * on what pHyp does. We keep interrupts disabled until - * after the mailbox has been properly configured. We assume - * basic stuff such as PSI link enable is already there. - * - * - FSP CMD Enable - * - FSP MMIO Enable - * - TCE Enable - * - Error response enable - * - * Clear all other error bits - */ - if (!psi->active) { - prerror("PSI: psi_init_for_fsp() called on inactive link!\n"); - unlock(&psi_lock); - return; - } - - reg = in_be64(psi->regs + PSIHB_CR); - reg |= PSIHB_CR_FSP_CMD_ENABLE; - reg |= PSIHB_CR_FSP_MMIO_ENABLE; - reg |= PSIHB_CR_FSP_ERR_RSP_ENABLE; - reg &= ~0x00000000ffffffffull; - out_be64(psi->regs + PSIHB_CR, reg); - psi_tce_enable(psi, enable_tce); - - unlock(&psi_lock); -} - void psi_set_external_irq_policy(bool policy) { psi_ext_irq_policy = policy; diff --git a/include/platform.h b/include/platform.h index 966f7041cb42..f17847ac0d60 100644 --- a/include/platform.h +++ b/include/platform.h @@ -79,6 +79,16 @@ struct platform_ocapi { struct dt_node; +/* + * Just for FSP platforms, allows us to partly decouple + * FSP specific code from core code. + */ +struct platform_psi { + void (*psihb_interrupt)(void); + void (*link_established)(void); + void (*fsp_interrupt)(void); +}; + /* * Each platform can provide a set of hooks * that can affect the generic code @@ -93,6 +103,11 @@ struct platform { */ const struct bmc_platform *bmc; + /* + * PSI handling code. FSP specific. + */ + const struct platform_psi *psi; + /* OpenCAPI platform-specific I2C information */ const struct platform_ocapi *ocapi; diff --git a/include/psi.h b/include/psi.h index ad56ce17eabd..1aca1afd1a02 100644 --- a/include/psi.h +++ b/include/psi.h @@ -273,6 +273,6 @@ extern void psi_fsp_link_in_use(struct psi *psi); #define EXTERNAL_IRQ_POLICY_SKIBOOT true extern void psi_set_external_irq_policy(bool policy); - +extern struct lock psi_lock; #endif /* __PSI_H */ diff --git a/platforms/ibm-fsp/common.c b/platforms/ibm-fsp/common.c index 055a75ce2119..ba20d5070353 100644 --- a/platforms/ibm-fsp/common.c +++ b/platforms/ibm-fsp/common.c @@ -261,3 +261,17 @@ int __attrconst fsp_heartbeat_time(void) /* Same as core/timer.c HEARTBEAT_DEFAULT_MS * 10 */ return 200 * 10; } + +static void fsp_psihb_interrupt(void) +{ + /* Poll the console buffers on any interrupt since we don't + * get send notifications + */ + fsp_console_poll(NULL); +} + +struct platform_psi fsp_platform_psi = { + .psihb_interrupt = fsp_psihb_interrupt, + .link_established = fsp_reinit_fsp, + .fsp_interrupt = fsp_interrupt, +}; diff --git a/platforms/ibm-fsp/firenze.c b/platforms/ibm-fsp/firenze.c index 1aedc0576632..6c25023235e7 100644 --- a/platforms/ibm-fsp/firenze.c +++ b/platforms/ibm-fsp/firenze.c @@ -209,6 +209,7 @@ static void firenze_init(void) DECLARE_PLATFORM(firenze) = { .name = "Firenze", + .psi = &fsp_platform_psi, .probe = firenze_probe, .init = firenze_init, .fast_reboot_init = fsp_console_reset, diff --git a/platforms/ibm-fsp/ibm-fsp.h b/platforms/ibm-fsp/ibm-fsp.h index c67202669a09..66139f0c06de 100644 --- a/platforms/ibm-fsp/ibm-fsp.h +++ b/platforms/ibm-fsp/ibm-fsp.h @@ -50,5 +50,6 @@ void vpd_preload(struct dt_node *hub_node); /* Platform heartbeat time */ int fsp_heartbeat_time(void); +extern struct platform_psi fsp_platform_psi; #endif /* __IBM_FSP_COMMON_H */ diff --git a/platforms/ibm-fsp/zz.c b/platforms/ibm-fsp/zz.c index 87d06417d02f..9e18e406a6f2 100644 --- a/platforms/ibm-fsp/zz.c +++ b/platforms/ibm-fsp/zz.c @@ -71,6 +71,7 @@ static void zz_init(void) DECLARE_PLATFORM(zz) = { .name = "ZZ", + .psi = &fsp_platform_psi, .probe = zz_probe, .init = zz_init, .fast_reboot_init = fsp_console_reset,