From patchwork Thu May 30 03:20:55 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Oliver O'Halloran X-Patchwork-Id: 1107510 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [203.11.71.2]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 45Dtkb6BRLz9sPk for ; Thu, 30 May 2019 13:44:55 +1000 (AEST) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="k22duhB/"; dkim-atps=neutral Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 45Dtkb1WFhzDqDt for ; Thu, 30 May 2019 13:44:55 +1000 (AEST) X-Original-To: skiboot@lists.ozlabs.org Delivered-To: skiboot@lists.ozlabs.org Authentication-Results: lists.ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=gmail.com (client-ip=2607:f8b0:4864:20::542; helo=mail-pg1-x542.google.com; envelope-from=oohall@gmail.com; receiver=) Authentication-Results: lists.ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: lists.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="k22duhB/"; dkim-atps=neutral Received: from mail-pg1-x542.google.com (mail-pg1-x542.google.com [IPv6:2607:f8b0:4864:20::542]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 45DtCG3YdKzDqQw for ; Thu, 30 May 2019 13:21:14 +1000 (AEST) Received: by mail-pg1-x542.google.com with SMTP id h2so1130606pgg.1 for ; Wed, 29 May 2019 20:21:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=vvr96G2aG6mSaiY5aZXVXlAercTB7Rzd0xc2NquRsuI=; b=k22duhB/caXbm7uh0gBcS7hqS9Sju5BRu2ZZ+sshZhIVuWxapGlbDPw1PxwPXUgKXE Q/88O6wxBFSPepyyPfmx9OveoC1ixr5kSTNiUdCF2JAeJ9k4oBkfI1q9f+RiadwsPvjU 8Qg4nJBzq/QoFKsGpdD5Hz+E6aE8NYqKuH0oEsuK8ICdYIOtCi0+5Y8LFkAwrY5j6VjG XLEYR/Qoq5iXCmRlKwfsKDHy1DCbnHDtNypPGdtWOwLzt8LkKVBuSPT6rVaHSmbvgLit uRovYIGhnnjp9noACotFR5oGfA6rjl+FVkMIAHQxk7UYOLVIgfpM4GLJpBHU9hWFiGk2 8hSA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=vvr96G2aG6mSaiY5aZXVXlAercTB7Rzd0xc2NquRsuI=; b=gSlNSnoxj0UxCFH14MjNVBpZfORzmZuQDzkBa8gEMfMV1MN4cWzeXI49A2J2A11b7Y Aot52kGtDUOOsPI8M3JfkOOS8eZzvncWDnawORqZ9LoCwCUEkKvgjx+g77dfBvj/i3rs UWyfh4pjm6HvAkEhBrlhKxLfMj+KYm3JTyYidT9xA+2ZOErwYDWLzL7ohu2TYDKxtyjE q9VTNSVbS7RIoIMUsvpaRmULPc+BMwR8USGEFQIPC/wV6hT45yV9W0O2VNvu5yqhOovU EJIZggJ5McKoHH9oVfyjLlkYyGDEyKhRA2pGR2uLOwyZcO4OprdRIIwb3i7cDAuI+bPt G3JQ== X-Gm-Message-State: APjAAAWvsck/9HgU0VuWP9/03EAvpMOtAV55CBpAMQuxL2AKSOGkY1OI tGj/YyWvZhxrDiY7lFt//cSVr2Ee X-Google-Smtp-Source: APXvYqz98Uq3FwWmmYHpRQEPFljjIqvaiyZtLIysD+0lNBxWsZfTFr8FvFwVV2KinxIl/ZRhdDj8UA== X-Received: by 2002:a63:554b:: with SMTP id f11mr1619170pgm.311.1559186472529; Wed, 29 May 2019 20:21:12 -0700 (PDT) Received: from wafer.ozlabs.ibm.com ([122.99.82.10]) by smtp.gmail.com with ESMTPSA id n2sm730696pgp.27.2019.05.29.20.21.10 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 29 May 2019 20:21:12 -0700 (PDT) From: Oliver O'Halloran To: skiboot@lists.ozlabs.org Date: Thu, 30 May 2019 13:20:55 +1000 Message-Id: <20190530032056.26355-2-oohall@gmail.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190530032056.26355-1-oohall@gmail.com> References: <20190530032056.26355-1-oohall@gmail.com> MIME-Version: 1.0 Subject: [Skiboot] [PATCH 2/3] hw/phb4: Set trace enable where it's used X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" The current LTSSM state was added to the PHB4 link trace output in 961547bceed3 ("phb4: Enhanced PCIe training tracing"). That patch split enabling the LTSSM state output from the rest of the tracing code in phb4_training_trace() to ensure that it would capture events from right after PERST is lifted. This is not really necessary since LTSSM state changes occur over milliseconds. We lose nothing by delaying the enable slightly so this patch moves it into phb4_training_trace() to keep the tracing code in one place. Signed-off-by: Oliver O'Halloran --- hw/phb4.c | 34 ++++++++++++++++++++++------------ 1 file changed, 22 insertions(+), 12 deletions(-) diff --git a/hw/phb4.c b/hw/phb4.c index cbe6b668f146..0c549e18f664 100644 --- a/hw/phb4.c +++ b/hw/phb4.c @@ -2658,11 +2658,21 @@ static bool phb4_link_optimal(struct pci_slot *slot, uint32_t *vdid) */ static void phb4_training_trace(struct phb4 *p) { - uint64_t reg, reglast = -1; + uint64_t trwctl, reg, reglast = -1; unsigned long now, start = mftb(); + bool enabled; + + /* + * Enable the DLP trace outputs. If we don't the LTSSM state in + * PHB_PCIE_DLP_TRAIN_CTL won't be updated and always reads zero. + */ + trwctl = phb4_read_reg(p, PHB_PCIE_DLP_TRWCTL); + enabled = !!(trwctl & PHB_PCIE_DLP_TRWCTL_EN); + if (!enabled) { + phb4_write_reg(p, PHB_PCIE_DLP_TRWCTL, + trwctl | PHB_PCIE_DLP_TRWCTL_EN); + } - if (!pci_tracing) - return; while(1) { now = mftb(); @@ -2684,6 +2694,13 @@ static void phb4_training_trace(struct phb4 *p) break; } } + + /* + * The trace enable bit is a clock gate for the tracing logic. Turn + * it off to save power if we're not using it otherwise. + */ + if (!enabled) + phb4_write_reg(p, PHB_PCIE_DLP_TRWCTL, trwctl); } /* @@ -2976,7 +2993,6 @@ static int64_t phb4_hreset(struct pci_slot *slot) static int64_t phb4_freset(struct pci_slot *slot) { struct phb4 *p = phb_to_phb4(slot->phb); - uint64_t reg; switch(slot->state) { case PHB4_SLOT_NORMAL: @@ -3007,17 +3023,11 @@ static int64_t phb4_freset(struct pci_slot *slot) /* Clear link errors before we deassert PERST */ phb4_err_clear_regb(p); - if (pci_tracing) { - /* Enable tracing */ - reg = in_be64(p->regs + PHB_PCIE_DLP_TRWCTL); - out_be64(p->regs + PHB_PCIE_DLP_TRWCTL, - reg | PHB_PCIE_DLP_TRWCTL_EN); - } - PHBDBG(p, "FRESET: Deassert\n"); phb4_assert_perst(slot, false); - phb4_training_trace(p); + if (pci_tracing) + phb4_training_trace(p) pci_slot_set_state(slot, PHB4_SLOT_LINK_START); return slot->ops.poll_link(slot);