From patchwork Sun Mar 24 17:25:38 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vaidyanathan Srinivasan X-Patchwork-Id: 1063317 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 44S47q3GPYz9sSG for ; Mon, 25 Mar 2019 04:26:47 +1100 (AEDT) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=linux.vnet.ibm.com Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 44S47p6ZWRzDqLl for ; Mon, 25 Mar 2019 04:26:46 +1100 (AEDT) X-Original-To: skiboot@lists.ozlabs.org Delivered-To: skiboot@lists.ozlabs.org Authentication-Results: lists.ozlabs.org; spf=none (mailfrom) smtp.mailfrom=linux.vnet.ibm.com (client-ip=148.163.156.1; helo=mx0a-001b2d01.pphosted.com; envelope-from=svaidy@linux.vnet.ibm.com; receiver=) Authentication-Results: lists.ozlabs.org; dmarc=none (p=none dis=none) header.from=linux.vnet.ibm.com Received: from mx0a-001b2d01.pphosted.com (mx0a-001b2d01.pphosted.com [148.163.156.1]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 44S47N052TzDqLj for ; Mon, 25 Mar 2019 04:26:23 +1100 (AEDT) Received: from pps.filterd (m0098394.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.16.0.27/8.16.0.27) with SMTP id x2OHNxN8097640 for ; Sun, 24 Mar 2019 13:26:21 -0400 Received: from e06smtp01.uk.ibm.com (e06smtp01.uk.ibm.com [195.75.94.97]) by mx0a-001b2d01.pphosted.com with ESMTP id 2re284evr9-1 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=NOT) for ; Sun, 24 Mar 2019 13:26:21 -0400 Received: from localhost by e06smtp01.uk.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! 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Violators will be prosecuted; (version=TLSv1/SSLv3 cipher=AES256-GCM-SHA384 bits=256/256) Sun, 24 Mar 2019 17:26:16 -0000 Received: from d06av24.portsmouth.uk.ibm.com (d06av24.portsmouth.uk.ibm.com [9.149.105.60]) by b06cxnps3074.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id x2OHQFaP58196154 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Sun, 24 Mar 2019 17:26:15 GMT Received: from d06av24.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 2854D42041; Sun, 24 Mar 2019 17:26:15 +0000 (GMT) Received: from d06av24.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id E43A24203F; Sun, 24 Mar 2019 17:26:13 +0000 (GMT) Received: from drishya.in.ibm.com (unknown [9.199.41.162]) by d06av24.portsmouth.uk.ibm.com (Postfix) with ESMTP; Sun, 24 Mar 2019 17:26:13 +0000 (GMT) From: Vaidyanathan Srinivasan To: Stewart Smith Date: Sun, 24 Mar 2019 22:55:38 +0530 X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190324172543.12625-1-svaidy@linux.vnet.ibm.com> References: <20190324172543.12625-1-svaidy@linux.vnet.ibm.com> MIME-Version: 1.0 X-TM-AS-GCONF: 00 x-cbid: 19032417-4275-0000-0000-0000031EB471 X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 19032417-4276-0000-0000-0000382D4407 Message-Id: <20190324172543.12625-4-svaidy@linux.vnet.ibm.com> X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:, , definitions=2019-03-24_10:, , signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 malwarescore=0 suspectscore=0 phishscore=0 bulkscore=0 spamscore=0 clxscore=1015 lowpriorityscore=0 mlxscore=0 impostorscore=0 mlxlogscore=822 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1810050000 definitions=main-1903240134 Subject: [Skiboot] [PATCH v3 3/8] chip: Fix pir_to_thread_id for fused cores X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: skiboot@lists.ozlabs.org, Michael Neuling Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" From: Benjamin Herrenschmidt pir_to_core_id() and pir_to_thread_id() are extensively used by the direct controls code and are expected to return the "normal" (non-fused, aka EC) core/thread IDs. Signed-off-by: Benjamin Herrenschmidt Signed-off-by: Michael Neuling --- core/chip.c | 6 +++--- include/chip.h | 7 +++++++ 2 files changed, 10 insertions(+), 3 deletions(-) diff --git a/core/chip.c b/core/chip.c index 2b9b6ef9..902327e1 100644 --- a/core/chip.c +++ b/core/chip.c @@ -37,12 +37,12 @@ uint32_t pir_to_chip_id(uint32_t pir) uint32_t pir_to_core_id(uint32_t pir) { - if (proc_gen == proc_gen_p9) + if (proc_gen == proc_gen_p9) { if (this_cpu()->is_fused_core) return P9_PIRFUSED2NORMALCOREID(pir); else return P9_PIR2COREID(pir); - else if (proc_gen == proc_gen_p8) + } else if (proc_gen == proc_gen_p8) return P8_PIR2COREID(pir); else return P7_PIR2COREID(pir); @@ -52,7 +52,7 @@ uint32_t pir_to_thread_id(uint32_t pir) { if (proc_gen == proc_gen_p9) { if (this_cpu()->is_fused_core) - return P9_PIR2FUSEDTHREADID(pir); + return P9_PIRFUSED2NORMALTHREADID(pir); else return P9_PIR2THREADID(pir); } else if (proc_gen == proc_gen_p8) diff --git a/include/chip.h b/include/chip.h index a73a52d7..afb2e3e9 100644 --- a/include/chip.h +++ b/include/chip.h @@ -133,6 +133,8 @@ (P9_PIR2FUSEDCOREID(pir) << 1) | \ (P9_PIR2FUSEDTHREADID(pir) & 1) +#define P9_PIRFUSED2NORMALTHREADID(pir) (((pir) >> 1) & 0x3) + /* P9 specific ones mostly used by XIVE */ #define P9_PIR2LOCALCPU(pir) ((pir) & 0xff) #define P9_PIRFROMLOCALCPU(chip, cpu) (((chip) << 8) | (cpu)) @@ -258,6 +260,11 @@ struct proc_chip { }; extern uint32_t pir_to_chip_id(uint32_t pir); + +/* + * Note: In P9 fused-core mode, these will return the "normal" + * core ID and thread ID (ie, thread ID 0..3) + */ extern uint32_t pir_to_core_id(uint32_t pir); extern uint32_t pir_to_thread_id(uint32_t pir);