From patchwork Sun Dec 9 14:17:43 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vaibhav Jain X-Patchwork-Id: 1009960 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 43CSzV1DTCz9s3l for ; Mon, 10 Dec 2018 01:20:38 +1100 (AEDT) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=linux.ibm.com Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 43CSzT6zgTzDr1K for ; Mon, 10 Dec 2018 01:20:37 +1100 (AEDT) Authentication-Results: lists.ozlabs.org; dmarc=none (p=none dis=none) header.from=linux.ibm.com X-Original-To: skiboot@lists.ozlabs.org Delivered-To: skiboot@lists.ozlabs.org Authentication-Results: lists.ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=linux.ibm.com (client-ip=148.163.158.5; helo=mx0a-001b2d01.pphosted.com; envelope-from=vaibhav@linux.ibm.com; receiver=) Authentication-Results: lists.ozlabs.org; dmarc=none (p=none dis=none) header.from=linux.ibm.com Received: from mx0a-001b2d01.pphosted.com (mx0b-001b2d01.pphosted.com [148.163.158.5]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 43CSxK5DvLzDr0t for ; Mon, 10 Dec 2018 01:18:45 +1100 (AEDT) Received: from pps.filterd (m0098416.ppops.net [127.0.0.1]) by mx0b-001b2d01.pphosted.com (8.16.0.22/8.16.0.22) with SMTP id wB9EErk0101070 for ; Sun, 9 Dec 2018 09:18:43 -0500 Received: from e06smtp03.uk.ibm.com (e06smtp03.uk.ibm.com [195.75.94.99]) by mx0b-001b2d01.pphosted.com with ESMTP id 2p8v3dwvk2-1 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=NOT) for ; Sun, 09 Dec 2018 09:18:43 -0500 Received: from localhost by e06smtp03.uk.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! 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Violators will be prosecuted; (version=TLSv1/SSLv3 cipher=AES256-GCM-SHA384 bits=256/256) Sun, 9 Dec 2018 14:18:40 -0000 Received: from d06av22.portsmouth.uk.ibm.com (d06av22.portsmouth.uk.ibm.com [9.149.105.58]) by b06cxnps3074.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id wB9EIcOi46596222 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=FAIL); Sun, 9 Dec 2018 14:18:38 GMT Received: from d06av22.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 6F2324C044; Sun, 9 Dec 2018 14:18:38 +0000 (GMT) Received: from d06av22.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 928AA4C040; Sun, 9 Dec 2018 14:18:35 +0000 (GMT) Received: from vajain21.in.ibm.com.com (unknown [9.102.1.240]) by d06av22.portsmouth.uk.ibm.com (Postfix) with ESMTP; Sun, 9 Dec 2018 14:18:35 +0000 (GMT) From: Vaibhav Jain To: Frederic Barrat , Andrew Donnellan , Christophe Lombard , Stewart Smith Date: Sun, 9 Dec 2018 19:47:43 +0530 X-Mailer: git-send-email 2.19.2 In-Reply-To: <20181209141744.4787-1-vaibhav@linux.ibm.com> References: <20181209141744.4787-1-vaibhav@linux.ibm.com> MIME-Version: 1.0 X-TM-AS-GCONF: 00 x-cbid: 18120914-0012-0000-0000-000002D6AD29 X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 18120914-0013-0000-0000-0000210C1C90 Message-Id: <20181209141744.4787-8-vaibhav@linux.ibm.com> X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:, , definitions=2018-12-09_05:, , signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 malwarescore=0 suspectscore=0 phishscore=0 bulkscore=0 spamscore=0 clxscore=1015 lowpriorityscore=0 mlxscore=0 impostorscore=0 mlxlogscore=999 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1810050000 definitions=main-1812090136 Subject: [Skiboot] [PATCH v2 7/8] phb4/capp: Implement sequence to disable CAPP and enable fast-reset X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: skiboot@lists.ozlabs.org Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" We implement h/w sequence to disable CAPP in disable_capi_mode() and with it also enable fast-reset for CAPI mode in phb4_set_capi_mode(). Sequence to disable CAPP is executed in three phases. The first two phase is implemented in disable_capi_mode() where we reset the CAPP registers followed by PEC registers to their init values. The final third final phase is to reset the PHB CAPI Compare/Mask Register and is done in phb4_init_ioda3(). The reason to move the PHB reset to phb4_init_ioda3() is because by the time Opal PCI reset state machine reaches this function the PHB is already un-fenced and its configuration registers accessible via mmio. Signed-off-by: Vaibhav Jain Reviewed-by: Andrew Donnellan --- Change-log: v2 Instead of using the 'PHB4_CAPP_REG_OFFSET' macro use the 'struct capp->capp_xscom_offset' member. --- hw/phb4.c | 77 ++++++++++++++++++++++++++++++++++++++++++++++++++++--- 1 file changed, 74 insertions(+), 3 deletions(-) diff --git a/hw/phb4.c b/hw/phb4.c index 447ba902..36353b74 100644 --- a/hw/phb4.c +++ b/hw/phb4.c @@ -3219,7 +3219,77 @@ static void disable_capi_mode(struct phb4 *p) PHBINF(p, "CAPP: Disabling CAPI mode\n"); - /* Implement procedure to disable CAPP based on h/w sequence */ + /* First Phase Reset CAPP Registers */ + /* CAPP about to be disabled mark TLBI_FENCED and tlbi_psl_is_dead */ + xscom_write(p->chip_id, capp->capp_xscom_offset + + CAPP_ERR_STATUS_CTRL, PPC_BIT(3) | PPC_BIT(4)); + + /* Flush SUE uOP1 Register */ + if (!(p->rev == PHB4_REV_NIMBUS_DD10)) + xscom_write(p->chip_id, capp->capp_xscom_offset + + FLUSH_SUE_UOP1, 0); + + /* Release DMA/STQ engines */ + xscom_write(p->chip_id, capp->capp_xscom_offset + + APC_FSM_READ_MASK, 0ull); + xscom_write(p->chip_id, capp->capp_xscom_offset + + XPT_FSM_RMM, 0ull); + + /* Disable snoop */ + xscom_write(p->chip_id, capp->capp_xscom_offset + SNOOP_CAPI_CONFIG, 0); + + /* Clear flush SUE state map register */ + xscom_write(p->chip_id, capp->capp_xscom_offset + + FLUSH_SUE_STATE_MAP, 0); + + /* Disable epoch timer */ + xscom_write(p->chip_id, capp->capp_xscom_offset + + EPOCH_RECOVERY_TIMERS_CTRL, 0); + + /* CAPP Transport Control Register */ + xscom_write(p->chip_id, capp->capp_xscom_offset + + TRANSPORT_CONTROL, PPC_BIT(15)); + + /* Disable snooping */ + xscom_write(p->chip_id, capp->capp_xscom_offset + + SNOOP_CONTROL, 0); + xscom_write(p->chip_id, capp->capp_xscom_offset + + SNOOP_CAPI_CONFIG, 0); + + /* APC Master PB Control Register - disable examining cResps */ + xscom_write(p->chip_id, capp->capp_xscom_offset + + APC_MASTER_PB_CTRL, 0); + + /* APC Master Config Register - de-select PHBs */ + xscom_write_mask(p->chip_id, capp->capp_xscom_offset + + APC_MASTER_CAPI_CTRL, 0, PPC_BITMASK(2, 3)); + + /* Clear all error registers */ + xscom_write(p->chip_id, capp->capp_xscom_offset + CAPP_ERR_RPT_CLR, 0); + xscom_write(p->chip_id, capp->capp_xscom_offset + CAPP_FIR, 0); + xscom_write(p->chip_id, capp->capp_xscom_offset + CAPP_FIR_ACTION0, 0); + xscom_write(p->chip_id, capp->capp_xscom_offset + CAPP_FIR_ACTION1, 0); + xscom_write(p->chip_id, capp->capp_xscom_offset + CAPP_FIR_MASK, 0); + + /* Second Phase Reset PEC/PHB Registers */ + + /* Reset the stack overrides if any */ + xscom_write(p->chip_id, p->pci_xscom + XPEC_PCI_PRDSTKOVR, 0); + xscom_write(p->chip_id, p->pe_xscom + + XPEC_NEST_READ_STACK_OVERRIDE, 0); + + /* PE Bus AIB Mode Bits. Disable Tracing. Leave HOL Blocking as it is */ + if (!(p->rev == PHB4_REV_NIMBUS_DD10) && p->index == CAPP1_PHB_INDEX) + xscom_write_mask(p->chip_id, + p->pci_xscom + XPEC_PCI_PBAIB_HW_CONFIG, 0, + PPC_BIT(30)); + + /* Reset for PCI to PB data movement */ + xscom_write_mask(p->chip_id, p->pe_xscom + XPEC_NEST_PBCQ_HW_CONFIG, + 0, XPEC_NEST_PBCQ_HW_CONFIG_PBINIT); + + /* Disable CAPP mode in PEC CAPP Control Register */ + xscom_write(p->chip_id, p->pe_xscom + XPEC_NEST_CAPP_CNTL, 0ull); } static int64_t phb4_creset(struct pci_slot *slot) @@ -4623,8 +4693,6 @@ static int64_t phb4_set_capi_mode(struct phb *phb, uint64_t mode, /* register notification on system shutdown */ opal_add_host_sync_notifier(&phb4_host_sync_reset, p); - /* Disable fast reboot for CAPP */ - disable_fast_reboot("CAPP being enabled"); } else { /* In case of an error mark the PHB detached */ capp->phb = NULL; @@ -4840,6 +4908,9 @@ static void phb4_init_ioda3(struct phb4 *p) /* Init_26 - CAPI Compare/Mask */ /* See enable_capi_mode() */ + /* if CAPP being disabled then reset CAPI Compare/Mask Register */ + if (p->flags & PHB4_CAPP_DISABLE) + out_be64(p->regs + PHB_CAPI_CMPM, 0); /* Init_27 - PCIE Outbound upper address */ out_be64(p->regs + PHB_M64_UPPER_BITS, 0);