From patchwork Sun Dec 9 14:17:40 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vaibhav Jain X-Patchwork-Id: 1009957 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 43CSyQ2DFcz9s3q for ; Mon, 10 Dec 2018 01:19:42 +1100 (AEDT) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=linux.ibm.com Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 43CSyQ0GSbzDr0m for ; Mon, 10 Dec 2018 01:19:42 +1100 (AEDT) Authentication-Results: lists.ozlabs.org; dmarc=none (p=none dis=none) header.from=linux.ibm.com X-Original-To: skiboot@lists.ozlabs.org Delivered-To: skiboot@lists.ozlabs.org Authentication-Results: lists.ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=linux.ibm.com (client-ip=148.163.156.1; helo=mx0a-001b2d01.pphosted.com; envelope-from=vaibhav@linux.ibm.com; receiver=) Authentication-Results: lists.ozlabs.org; dmarc=none (p=none dis=none) header.from=linux.ibm.com Received: from mx0a-001b2d01.pphosted.com (mx0a-001b2d01.pphosted.com [148.163.156.1]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 43CSx56rWkzDr0p for ; Mon, 10 Dec 2018 01:18:33 +1100 (AEDT) Received: from pps.filterd (m0098396.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.16.0.22/8.16.0.22) with SMTP id wB9EEk0I067134 for ; Sun, 9 Dec 2018 09:18:31 -0500 Received: from e06smtp03.uk.ibm.com (e06smtp03.uk.ibm.com [195.75.94.99]) by mx0a-001b2d01.pphosted.com with ESMTP id 2p8uqw6b2y-1 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=NOT) for ; Sun, 09 Dec 2018 09:18:31 -0500 Received: from localhost by e06smtp03.uk.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! 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Violators will be prosecuted; (version=TLSv1/SSLv3 cipher=AES256-GCM-SHA384 bits=256/256) Sun, 9 Dec 2018 14:18:27 -0000 Received: from d06av22.portsmouth.uk.ibm.com (d06av22.portsmouth.uk.ibm.com [9.149.105.58]) by b06cxnps4074.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id wB9EIP6o4063602 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=FAIL); Sun, 9 Dec 2018 14:18:25 GMT Received: from d06av22.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 6FE8D4C04A; Sun, 9 Dec 2018 14:18:25 +0000 (GMT) Received: from d06av22.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id DA1644C040; Sun, 9 Dec 2018 14:18:22 +0000 (GMT) Received: from vajain21.in.ibm.com.com (unknown [9.102.1.240]) by d06av22.portsmouth.uk.ibm.com (Postfix) with ESMTP; Sun, 9 Dec 2018 14:18:22 +0000 (GMT) From: Vaibhav Jain To: Frederic Barrat , Andrew Donnellan , Christophe Lombard , Stewart Smith Date: Sun, 9 Dec 2018 19:47:40 +0530 X-Mailer: git-send-email 2.19.2 In-Reply-To: <20181209141744.4787-1-vaibhav@linux.ibm.com> References: <20181209141744.4787-1-vaibhav@linux.ibm.com> MIME-Version: 1.0 X-TM-AS-GCONF: 00 x-cbid: 18120914-0012-0000-0000-000002D6AD27 X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 18120914-0013-0000-0000-0000210C1C8D Message-Id: <20181209141744.4787-5-vaibhav@linux.ibm.com> X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:, , definitions=2018-12-09_05:, , signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 malwarescore=0 suspectscore=0 phishscore=0 bulkscore=0 spamscore=0 clxscore=1015 lowpriorityscore=0 mlxscore=0 impostorscore=0 mlxlogscore=999 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1810050000 definitions=main-1812090136 Subject: [Skiboot] [PATCH v2 4/8] phb4/capp: Update and re-factor phb4_set_capi_mode() X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: skiboot@lists.ozlabs.org Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" Presently phb4_set_capi_mode() performs certain CAPP checks like, checking of CAPP ucode loaded or checks if CAPP is still in recovery, even when the requested mode is to switch to PCI mode. Hence this patch updates and re-factors phb4_set_capi_mode() to make sure CAPP related checks are only performed when request to enable CAPP is made by mode==OPAL_PHB_CAPI_MODE_CAPI/DMA_TVT1. We also update other possible modes requests to return a more appropriate status code based on if CAPP is activated or not. Signed-off-by: Vaibhav Jain Reviewed-by: Andrew Donnellan --- Change-log: v2: Using 'struct capp* instead of global 'capi_lock' to indicate that CAPP is now attached to a PHB [Andrew] Code formatting that removed the use of a confusing tertiary operator. [Andrew] --- hw/phb4.c | 93 ++++++++++++++++++++++++++++++++++--------------------- 1 file changed, 57 insertions(+), 36 deletions(-) diff --git a/hw/phb4.c b/hw/phb4.c index 5819ad0b..df483e27 100644 --- a/hw/phb4.c +++ b/hw/phb4.c @@ -4436,54 +4436,75 @@ static int64_t phb4_set_capi_mode(struct phb *phb, uint64_t mode, struct proc_chip *chip = get_chip(p->chip_id); struct capp *capp = phb->capp; uint64_t reg, ret; - uint32_t offset; if (capp == NULL) return OPAL_UNSUPPORTED; - if (!capp_ucode_loaded(chip, p->index)) { - PHBERR(p, "CAPP: ucode not loaded\n"); - return OPAL_RESOURCE; - } - - /* mark the capp attached to the phb */ - capp->phb = phb; - capp->attached_pe = pe_number; + switch (mode) { - offset = PHB4_CAPP_REG_OFFSET(p); - xscom_read(p->chip_id, CAPP_ERR_STATUS_CTRL + offset, ®); - if ((reg & PPC_BIT(5))) { - PHBERR(p, "CAPP: recovery failed (%016llx)\n", reg); - return OPAL_HARDWARE; - } else if ((reg & PPC_BIT(0)) && (!(reg & PPC_BIT(1)))) { - PHBDBG(p, "CAPP: recovery in progress\n"); - return OPAL_BUSY; - } + case OPAL_PHB_CAPI_MODE_DMA: /* Enabled by default on p9 */ + case OPAL_PHB_CAPI_MODE_SNOOP_ON: + /* nothing to do on P9 if CAPP is alreay enabled */ + ret = phb->capp->phb ? OPAL_SUCCESS : OPAL_UNSUPPORTED; + break; - switch (mode) { - case OPAL_PHB_CAPI_MODE_CAPI: - ret = enable_capi_mode(p, pe_number, - CAPP_MAX_STQ_ENGINES | - CAPP_MIN_DMA_READ_ENGINES); - disable_fast_reboot("CAPP being enabled"); + case OPAL_PHB_CAPI_MODE_SNOOP_OFF: + case OPAL_PHB_CAPI_MODE_PCIE: /* Not supported at the moment */ + ret = phb->capp->phb ? OPAL_UNSUPPORTED : OPAL_SUCCESS; break; + + case OPAL_PHB_CAPI_MODE_CAPI: /* Fall Through */ case OPAL_PHB_CAPI_MODE_DMA_TVT1: - ret = enable_capi_mode(p, pe_number, - CAPP_MIN_STQ_ENGINES | - CAPP_MAX_DMA_READ_ENGINES); - disable_fast_reboot("CAPP being enabled"); - break; - case OPAL_PHB_CAPI_MODE_SNOOP_ON: - /* nothing to do P9 if CAPP is alreay enabled */ - ret = OPAL_SUCCESS; + /* Check if ucode is available */ + if (!capp_ucode_loaded(chip, p->index)) { + PHBERR(p, "CAPP: ucode not loaded\n"); + ret = OPAL_RESOURCE; + break; + } + + xscom_read(p->chip_id, CAPP_ERR_STATUS_CTRL + offset, ®); + if ((reg & PPC_BIT(5))) { + PHBERR(p, "CAPP: recovery failed (%016llx)\n", reg); + ret = OPAL_HARDWARE; + break; + } else if ((reg & PPC_BIT(0)) && (!(reg & PPC_BIT(1)))) { + PHBDBG(p, "CAPP: recovery in progress\n"); + ret = OPAL_BUSY; + break; + } + + /* + * Mark the CAPP attached to the PHB right away so that + * if a MCE happens during CAPP init we can handle it. + * In case of an error in CAPP init we remove the PHB + * from the attached_mask later. + */ + capp->phb = phb; + capp->attached_pe = pe_number; + + if (mode == OPAL_PHB_CAPI_MODE_DMA_TVT1) + ret = enable_capi_mode(p, pe_number, + CAPP_MIN_STQ_ENGINES | + CAPP_MAX_DMA_READ_ENGINES); + + else + ret = enable_capi_mode(p, pe_number, + CAPP_MAX_STQ_ENGINES | + CAPP_MIN_DMA_READ_ENGINES); + if (ret == OPAL_SUCCESS) { + /* Disable fast reboot for CAPP */ + disable_fast_reboot("CAPP being enabled"); + } else { + /* In case of an error mark the PHB detached */ + capp->phb = NULL; + capp->attached_pe = phb4_get_reserved_pe_number(phb); + } break; - case OPAL_PHB_CAPI_MODE_PCIE: /* shouldn't be called on p9*/ - case OPAL_PHB_CAPI_MODE_DMA: /* Enabled by default on p9 */ - case OPAL_PHB_CAPI_MODE_SNOOP_OFF: /* shouldn't be called on p9*/ default: ret = OPAL_UNSUPPORTED; - } + break; + }; return ret; }