From patchwork Sun Dec 9 14:17:38 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vaibhav Jain X-Patchwork-Id: 1009955 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 43CSxn2lxnz9s3Z for ; Mon, 10 Dec 2018 01:19:09 +1100 (AEDT) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=linux.ibm.com Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 43CSxm6NpfzDr0d for ; Mon, 10 Dec 2018 01:19:08 +1100 (AEDT) Authentication-Results: lists.ozlabs.org; dmarc=none (p=none dis=none) header.from=linux.ibm.com X-Original-To: skiboot@lists.ozlabs.org Delivered-To: skiboot@lists.ozlabs.org Authentication-Results: lists.ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=linux.ibm.com (client-ip=148.163.156.1; helo=mx0a-001b2d01.pphosted.com; envelope-from=vaibhav@linux.ibm.com; receiver=) Authentication-Results: lists.ozlabs.org; dmarc=none (p=none dis=none) header.from=linux.ibm.com Received: from mx0a-001b2d01.pphosted.com (mx0a-001b2d01.pphosted.com [148.163.156.1]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 43CSwy21S2zDr0s for ; Mon, 10 Dec 2018 01:18:26 +1100 (AEDT) Received: from pps.filterd (m0098393.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.16.0.22/8.16.0.22) with SMTP id wB9EEsU2022872 for ; Sun, 9 Dec 2018 09:18:24 -0500 Received: from e06smtp04.uk.ibm.com (e06smtp04.uk.ibm.com [195.75.94.100]) by mx0a-001b2d01.pphosted.com with ESMTP id 2p8v24e1k4-1 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=NOT) for ; Sun, 09 Dec 2018 09:18:24 -0500 Received: from localhost by e06smtp04.uk.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! 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Violators will be prosecuted; (version=TLSv1/SSLv3 cipher=AES256-GCM-SHA384 bits=256/256) Sun, 9 Dec 2018 14:18:18 -0000 Received: from d06av22.portsmouth.uk.ibm.com (d06av22.portsmouth.uk.ibm.com [9.149.105.58]) by b06cxnps3075.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id wB9EIG4c59900048 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=FAIL); Sun, 9 Dec 2018 14:18:17 GMT Received: from d06av22.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id D2C474C044; Sun, 9 Dec 2018 14:18:16 +0000 (GMT) Received: from d06av22.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 48E404C04E; Sun, 9 Dec 2018 14:18:14 +0000 (GMT) Received: from vajain21.in.ibm.com.com (unknown [9.102.1.240]) by d06av22.portsmouth.uk.ibm.com (Postfix) with ESMTP; Sun, 9 Dec 2018 14:18:13 +0000 (GMT) From: Vaibhav Jain To: Frederic Barrat , Andrew Donnellan , Christophe Lombard , Stewart Smith Date: Sun, 9 Dec 2018 19:47:38 +0530 X-Mailer: git-send-email 2.19.2 In-Reply-To: <20181209141744.4787-1-vaibhav@linux.ibm.com> References: <20181209141744.4787-1-vaibhav@linux.ibm.com> MIME-Version: 1.0 X-TM-AS-GCONF: 00 x-cbid: 18120914-0016-0000-0000-000002341A39 X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 18120914-0017-0000-0000-0000328C3E06 Message-Id: <20181209141744.4787-3-vaibhav@linux.ibm.com> X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:, , definitions=2018-12-09_05:, , signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 malwarescore=0 suspectscore=0 phishscore=0 bulkscore=0 spamscore=0 clxscore=1015 lowpriorityscore=0 mlxscore=0 impostorscore=0 mlxlogscore=999 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1810050000 definitions=main-1812090136 Subject: [Skiboot] [PATCH v2 2/8] core/pci: Introduce a new pci_slot_op named completed_sm_run() X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: skiboot@lists.ozlabs.org Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" At times we need to perform some cleanup activities when the Opal PCI state machine that perform creset/freset/hreset (driven by pci_slot_ops->run_sm which) of a slot completes. One example can be to mark CAPP attached to a PHB, as deactivated when creset/freset of a CAPI card slot is completed. However the calls to pci_slot_ops->run_sm() is scattered through out the code and patching each call site to check for the return value and perform custom cleanup tacks is difficult. Hence this patch introduces a new pci_slot_ops named completed_sm_run() which should be called when pci_slot_ops->run_sm() determines that the reset state machine is complete. This provides a more centralized way to handle slot related cleanup activities. Signed-off-by: Vaibhav Jain Reviewed-by: Andrew Donnellan Reviewed-by: Christophe Lombard --- Change-log v2: Update the callback signature to return a int64_t back to caller. [Andrew] --- core/pci-slot.c | 6 +++++- include/pci-slot.h | 1 + 2 files changed, 6 insertions(+), 1 deletion(-) diff --git a/core/pci-slot.c b/core/pci-slot.c index 71d2769e..497d0a47 100644 --- a/core/pci-slot.c +++ b/core/pci-slot.c @@ -104,9 +104,13 @@ static int64_t pci_slot_run_sm(struct pci_slot *slot) prlog(PR_ERR, PCI_SLOT_PREFIX "Invalid state %08x\n", slot->id, slot->state); pci_slot_set_state(slot, PCI_SLOT_STATE_NORMAL); - return OPAL_HARDWARE; + ret = OPAL_HARDWARE; } + /* Notify about the pci slot state machine completion */ + if (ret <= 0 && slot->ops.completed_sm_run) + slot->ops.completed_sm_run(slot, ret); + return ret; } diff --git a/include/pci-slot.h b/include/pci-slot.h index cd757535..708374b6 100644 --- a/include/pci-slot.h +++ b/include/pci-slot.h @@ -110,6 +110,7 @@ struct pci_slot_ops { int64_t (*freset)(struct pci_slot *slot); int64_t (*hreset)(struct pci_slot *slot); int64_t (*run_sm)(struct pci_slot *slot); + int64_t (*completed_sm_run)(struct pci_slot *slot, uint64_t err); /* Auxillary functions */ void (*add_properties)(struct pci_slot *slot, struct dt_node *np);