From patchwork Wed Apr 11 01:42:09 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Balbir Singh X-Patchwork-Id: 896998 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) (using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 40LRch1k39z9s0b for ; Wed, 11 Apr 2018 11:42:44 +1000 (AEST) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="OD2Rqwxs"; dkim-atps=neutral Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 40LRcg605lzF1QM for ; Wed, 11 Apr 2018 11:42:43 +1000 (AEST) Authentication-Results: lists.ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: lists.ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="OD2Rqwxs"; dkim-atps=neutral X-Original-To: skiboot@lists.ozlabs.org Delivered-To: skiboot@lists.ozlabs.org Authentication-Results: lists.ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=gmail.com (client-ip=2607:f8b0:400e:c01::244; helo=mail-pl0-x244.google.com; envelope-from=bsingharora@gmail.com; receiver=) Authentication-Results: lists.ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: lists.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="OD2Rqwxs"; dkim-atps=neutral Received: from mail-pl0-x244.google.com (mail-pl0-x244.google.com [IPv6:2607:f8b0:400e:c01::244]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 40LRcD5VYlzF1QH for ; Wed, 11 Apr 2018 11:42:19 +1000 (AEST) Received: by mail-pl0-x244.google.com with SMTP id e22-v6so173994plj.12 for ; Tue, 10 Apr 2018 18:42:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id; bh=P60vzHs+qspPWHqpaNLbLd6qEanOn09n3HHc+bXcsvU=; b=OD2Rqwxsmr421v9N/zNH83N9eZIiXOSTbKpwJK+FlJ+Y5waqCkR5cjOyYCZXt9xI9+ mZ30gTw++VVs0krEs/5RczkRMCIOBQup+dtQe1TY2jw0989iAe5T7Zmxx+PNiSZBA2Ir 5Lb057pPLIJsdVpV71F5bu/JZuNBoyMq+QQyFV7Jr+NbWHUaUMD0Jw9nUtOkkTZXNAoQ X1o/Fn8xYFDAQ28zxROW7YrRYY/GgSBXEhAcE9XwnEKwwFmaX75DqrW3O/N+Y8wBHAf0 ENbEUltiouqIt0mWQpX/FyrI+agKyn13VaK6CMhsuXiKnfm5w+40Z9/qdSiAwABgvs21 JQjA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=P60vzHs+qspPWHqpaNLbLd6qEanOn09n3HHc+bXcsvU=; b=po3wCTZIjbXnAbuVnvnzLDLrcky7ASknNz6GL7jn9njQNPSs0SHdYQ1sTiv39cRX4i bAdehjG7lkRapG1C7F+f3f0Xr5LboX0ftbXOsZj8QPTRGBI07Cm+LQnfHK4TK1MrGOGS tQH0skDQmYXZ4MMup73q/S57YhKLPM1Yg4EFmLHVjo20P3yvwNSKXZhn6E0PTnZ7Vy9M qoT+UWoquBBnh7CmoPR2+2TNtgP4oaO657h/yVMZtxUEZ4LveLipx3k2moUiW8YPGaWi QrJ7RLPsbGqaOnII3qerO7uFDJJkL5XqaINCe6SMVZDftzzgmCVp6RY5504YDpROIGeN Buog== X-Gm-Message-State: ALQs6tBhjB/DzqY1EuKBCIrekH4kQFHXaeG4mRgIR3tSiu4x/2DrKHmK tkN36ebDOJ7tV9eVfaRl3xr6mDAj X-Google-Smtp-Source: AIpwx48bT6FeD6ogopKII3z28gq6WgYiHLr6LtTBmQsS03StDOiTcMSCG/be/ekQi0ok4dur70mOyQ== X-Received: by 2002:a17:902:144:: with SMTP id 62-v6mr2878276plb.202.1523410937923; Tue, 10 Apr 2018 18:42:17 -0700 (PDT) Received: from balbir.ozlabs.ibm.com ([122.99.82.10]) by smtp.googlemail.com with ESMTPSA id d64sm53546pfa.80.2018.04.10.18.42.15 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 10 Apr 2018 18:42:17 -0700 (PDT) From: Balbir Singh To: skiboot@lists.ozlabs.org Date: Wed, 11 Apr 2018 11:42:09 +1000 Message-Id: <20180411014209.19178-1-bsingharora@gmail.com> X-Mailer: git-send-email 2.13.6 Subject: [Skiboot] [PATCH v2] mambo/mambo_utils.tcl: Inject an MCE at a specified address X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.26 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: stewart@linux.vnet.ibm.com MIME-Version: 1.0 Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" Currently we don't support injecting an MCE on a specific address. This is useful for testing functionality like memcpy_mcsafe() (see https://patchwork.ozlabs.org/cover/893339/) This patch refactors exc_mce into setup_mce and exc_mce. setup_mce is generally useful to setup a MCE context with variables DSISR, SRR1 and DAR. setup_mce supports setting up dsisr as a new function argument. It's useful when we want to set up both the cause and DSIR. The core of the functionality is a routine called inject_mce_ue_on_addr, which takes an addr argument and injects an MCE (load/store with UE) when the specified address is accessed by code. This functionality can easily be enhanced to cover instruction UE's as well. Signed-off-by: Balbir Singh --- Changelog v2 - Reuse cause, don't add DSISR for d-side - Test with nick's pending refactoring external/mambo/mambo_utils.tcl | 25 ++++++++++++++++++++++--- 1 file changed, 22 insertions(+), 3 deletions(-) diff --git a/external/mambo/mambo_utils.tcl b/external/mambo/mambo_utils.tcl index 7a27f0f4..9c6a329c 100644 --- a/external/mambo/mambo_utils.tcl +++ b/external/mambo/mambo_utils.tcl @@ -442,11 +442,12 @@ proc mce_trigger { args } { # # Default with no arguments is a recoverable i-side TLB multi-hit # Other options: -# d_side=1 cause=0x80 - recoverable d-side SLB multi-hit +# d_side=1 dsisr=0x80 - recoverable d-side SLB multi-hit +# d_side=1 dsisr=0x8000 - ue error on instruction fetch # d_side=0 cause=0xd - unrecoverable i-side async store timeout (POWER9 only) # d_side=0 cause=0x1 - unrecoverable i-side ifetch # -proc exc_mce { { d_side 0 } { cause 0x5 } { recoverable 1 } } { +proc setup_mce { { d_side 0 } { cause 0x5 } { recoverable 1 }} { variable SRR1 variable DSISR variable DAR @@ -466,7 +467,6 @@ proc exc_mce { { d_side 0 } { cause 0x5 } { recoverable 1 } } { set msr_ri 0x0 } - # recoverable d-side SLB multihit if { $d_side } { set is_dside 1 set SRR1_mc_cause 0x0 @@ -486,7 +486,10 @@ proc exc_mce { { d_side 0 } { cause 0x5 } { recoverable 1 } } { set SRR1 [expr $SRR1 | ((($SRR1_mc_cause >> 2) & 0x1) << (63-43))] set SRR1 [expr $SRR1 | ((($SRR1_mc_cause >> 1) & 0x1) << (63-44))] set SRR1 [expr $SRR1 | ((($SRR1_mc_cause >> 0) & 0x1) << (63-45))] +} +proc exc_mce { { d_side 0 } { cause 0x5 } { recoverable 1 }} { + setup_mce $d_side $cause $recoverable if { [current_insn] in { "stop" "nap" "sleep" "winkle" } } { # mambo has a quirk that interrupts from idle wake immediately mysim trigger set pc 0x200 "mce_trigger" @@ -526,6 +529,22 @@ proc inject_mce { } { mysim trigger clear pc $pc ; list } +# +# We've stopped at addr and we need to inject the mce and continue +# +proc trigger_mce_ue_addr {args} { + set addr [lindex [lindex $args 0] 1] + mysim trigger clear memory system rw $addr $addr + setup_mce 0x1 0x8000 0x1 + mysim trigger set pc 0x200 "mce_trigger" + mysim cpu 0 interrupt MachineCheck + mce_trigger +} + +proc inject_mce_ue_on_addr {addr} { + mysim trigger set memory system rw $addr $addr 1 "trigger_mce_ue_addr" +} + # inject and step over one instruction, and repeat. proc inject_mce_step { {nr 1} } { for { set i 0 } { $i < $nr } { incr i 1 } {