From patchwork Thu Jun 22 16:22:07 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Benjamin Herrenschmidt X-Patchwork-Id: 779593 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) (using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3wtn2t1GVJz9sNv for ; Fri, 23 Jun 2017 02:24:06 +1000 (AEST) Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 3wtn2r6wWXzDr0T for ; Fri, 23 Jun 2017 02:24:04 +1000 (AEST) X-Original-To: skiboot@lists.ozlabs.org Delivered-To: skiboot@lists.ozlabs.org Received: from gate.crashing.org (gate.crashing.org [63.228.1.57]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 3wtn1s2trfzDr6F for ; Fri, 23 Jun 2017 02:23:13 +1000 (AEST) Received: from pasglop.austin.ibm.com (localhost.localdomain [127.0.0.1]) by gate.crashing.org (8.14.1/8.13.8) with ESMTP id v5MGMaCQ024844; Thu, 22 Jun 2017 11:23:02 -0500 From: Benjamin Herrenschmidt To: skiboot@lists.ozlabs.org Date: Thu, 22 Jun 2017 11:22:07 -0500 Message-Id: <20170622162225.26344-6-benh@kernel.crashing.org> X-Mailer: git-send-email 2.9.4 In-Reply-To: <20170622162225.26344-1-benh@kernel.crashing.org> References: <20170622162225.26344-1-benh@kernel.crashing.org> Subject: [Skiboot] [PATCH 06/24] phb4: Properly mask out link down errors during reset X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" From: Russell Currey Signed-off-by: Russell Currey --- hw/phb4.c | 27 ++++++++++++++++++++------- 1 file changed, 20 insertions(+), 7 deletions(-) diff --git a/hw/phb4.c b/hw/phb4.c index a2641b8..3ee618e 100644 --- a/hw/phb4.c +++ b/hw/phb4.c @@ -1892,13 +1892,17 @@ static void phb4_prepare_link_change(struct pci_slot *slot, bool is_up) /* Don't block PCI-CFG */ p->flags &= ~PHB4_CFG_BLOCKED; - /* Clear error link enable & error link down kill enable */ - out_be64(p->regs + PHB_PCIE_MISC_STRAP, 0); - - /* Disable all error status indicators that trigger irqs */ - out_be64(p->regs + PHB_REGB_ERR_INF_ENABLE, 0); - out_be64(p->regs + PHB_REGB_ERR_ERC_ENABLE, 0); - out_be64(p->regs + PHB_REGB_ERR_FAT_ENABLE, 0); + /* Re-enable link down errors */ + out_be64(p->regs + PHB_PCIE_MISC_STRAP, + 0x0000060000000000ull); + + /* Re-enable error status indicators that trigger irqs */ + out_be64(p->regs + PHB_REGB_ERR_INF_ENABLE, + 0x2130006efca8bc00ull); + out_be64(p->regs + PHB_REGB_ERR_ERC_ENABLE, + 0x0000000000000000ull); + out_be64(p->regs + PHB_REGB_ERR_FAT_ENABLE, + 0xde8fff91035743ffull); /* * We might lose the bus numbers during the reset operation @@ -1919,6 +1923,15 @@ static void phb4_prepare_link_change(struct pci_slot *slot, bool is_up) reg32 |= PCIECAP_AER_CE_RECVR_ERR; phb4_pcicfg_write32(&p->phb, 0, p->aercap + PCIECAP_AER_CE_MASK, reg32); + + /* Clear error link enable & error link down kill enable */ + out_be64(p->regs + PHB_PCIE_MISC_STRAP, 0); + + /* Disable all error status indicators that trigger irqs */ + out_be64(p->regs + PHB_REGB_ERR_INF_ENABLE, 0); + out_be64(p->regs + PHB_REGB_ERR_ERC_ENABLE, 0); + out_be64(p->regs + PHB_REGB_ERR_FAT_ENABLE, 0); + /* Block PCI-CFG access */ p->flags |= PHB4_CFG_BLOCKED; }