From patchwork Fri Jun 9 06:06:04 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Russell Currey X-Patchwork-Id: 773665 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) (using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3wkWz51RlKz9s72 for ; Fri, 9 Jun 2017 16:07:13 +1000 (AEST) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=messagingengine.com header.i=@messagingengine.com header.b="Yg1SrVVd"; dkim-atps=neutral Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 3wkWz50NPvzDqND for ; Fri, 9 Jun 2017 16:07:13 +1000 (AEST) Authentication-Results: lists.ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=messagingengine.com header.i=@messagingengine.com header.b="Yg1SrVVd"; dkim-atps=neutral X-Original-To: skiboot@lists.ozlabs.org Delivered-To: skiboot@lists.ozlabs.org Received: from out1-smtp.messagingengine.com (out1-smtp.messagingengine.com [66.111.4.25]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 3wkWyF1G4lzDqLM for ; Fri, 9 Jun 2017 16:06:29 +1000 (AEST) Authentication-Results: lists.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=messagingengine.com header.i=@messagingengine.com header.b="Yg1SrVVd"; dkim-atps=neutral Received: from compute6.internal (compute6.nyi.internal [10.202.2.46]) by mailout.nyi.internal (Postfix) with ESMTP id 85B1A20BB1; Fri, 9 Jun 2017 02:06:26 -0400 (EDT) Received: from frontend1 ([10.202.2.160]) by compute6.internal (MEProxy); Fri, 09 Jun 2017 02:06:26 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:date:from:in-reply-to:message-id :references:subject:to:x-me-sender:x-me-sender:x-sasl-enc :x-sasl-enc; s=fm1; bh=BF1ew2jBtHuJ+8MXwoBDWcxJiyhCQUfVCa84OKVga jU=; b=Yg1SrVVdJe7w8Fio96U9wvCo8RBbKmZDNGlDvP4xIbqmSh9a4W1teWsNb hLDuQapcUBWSVg4nIQY3mJScZu+eIfHy6nz8V3Iu9OqfriX97vN+YVqEdVs/b1or sDplUEFqUJ2cQUQOfGOSDlm74n9Yu0lhhieaQirxwrQzLPWPzBkYQP0U6ee6vz2p 2LhS5wUuC5yREZCK1GZP07y7w8A9jRMVxQA3GsFS2IoKaii2Ka3ceHblRicTSmHV 2y86IQQawu8csABUZUQGZpVT6asVZ0HoG97884E9KjUT3PALJ+7oorKP2hHn55RF 5HbQfuLO9zsuDF6KkiDipQsgBq09Q== X-ME-Sender: X-Sasl-enc: R9McNgPY2DbomM4FgQzpMSYd0FUFkP77gW9cbDELGMiA 1496988385 Received: from snap.ozlabs.ibm.com (unknown [122.99.82.10]) by mail.messagingengine.com (Postfix) with ESMTPA id 3235C7E545; Fri, 9 Jun 2017 02:06:24 -0400 (EDT) From: Russell Currey To: skiboot@lists.ozlabs.org Date: Fri, 9 Jun 2017 16:06:04 +1000 Message-Id: <20170609060606.17796-4-ruscur@russell.cc> X-Mailer: git-send-email 2.13.1 In-Reply-To: <20170609060606.17796-1-ruscur@russell.cc> References: <20170609060606.17796-1-ruscur@russell.cc> Subject: [Skiboot] [PATCH 3/5] phb4: Mask link down errors during reset X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" During a hot reset the PCI link will drop, so we need to mask link down events to prevent unnecessary errors. Signed-off-by: Russell Currey --- hw/phb4.c | 8 ++++++++ include/phb4-regs.h | 2 ++ 2 files changed, 10 insertions(+) diff --git a/hw/phb4.c b/hw/phb4.c index 3957a051..c0bc634c 100644 --- a/hw/phb4.c +++ b/hw/phb4.c @@ -1818,6 +1818,14 @@ static void phb4_prepare_link_change(struct pci_slot *slot, bool is_up) /* Don't block PCI-CFG */ p->flags &= ~PHB4_CFG_BLOCKED; + /* Clear error link enable & error link down kill enable */ + out_be64(p->regs + PHB_PCIE_MISC_STRAP, 0); + + /* Disable all error status indicators that trigger irqs */ + out_be64(p->regs + PHB_REGB_ERR_INF_ENABLE, 0); + out_be64(p->regs + PHB_REGB_ERR_ERC_ENABLE, 0); + out_be64(p->regs + PHB_REGB_ERR_FAT_ENABLE, 0); + /* * We might lose the bus numbers during the reset operation * and we need to restore them. Otherwise, some adapters (e.g. diff --git a/include/phb4-regs.h b/include/phb4-regs.h index 92bee88f..1ccef3a0 100644 --- a/include/phb4-regs.h +++ b/include/phb4-regs.h @@ -288,6 +288,8 @@ #define PHB_PCIE_LANE_EQ_CNTL21 0x1AF8 #define PHB_PCIE_LANE_EQ_CNTL22 0x1B00 /* DD1 only */ #define PHB_PCIE_LANE_EQ_CNTL23 0x1B08 /* DD1 only */ +#define PHB_PCIE_TRACE_CTRL 0x1B20 +#define PHB_PCIE_MISC_STRAP 0x1B30 #define PHB_REGB_ERR_STATUS 0x1C00 #define PHB_REGB_ERR1_STATUS 0x1C08