From patchwork Mon Jun 5 22:59:23 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Benjamin Herrenschmidt X-Patchwork-Id: 771503 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) (using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3whVgH1MVvz9s5L for ; Tue, 6 Jun 2017 09:01:31 +1000 (AEST) Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 3whVgH0NGXzDqLq for ; Tue, 6 Jun 2017 09:01:31 +1000 (AEST) X-Original-To: skiboot@lists.ozlabs.org Delivered-To: skiboot@lists.ozlabs.org Received: from gate.crashing.org (gate.crashing.org [63.228.1.57]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 3whVg368jfzDqKy for ; Tue, 6 Jun 2017 09:01:19 +1000 (AEST) Received: from pasglop.au.ibm.com (localhost.localdomain [127.0.0.1]) by gate.crashing.org (8.14.1/8.13.8) with ESMTP id v55MxVn7025839; Mon, 5 Jun 2017 17:59:56 -0500 From: Benjamin Herrenschmidt To: skiboot@lists.ozlabs.org Date: Tue, 6 Jun 2017 08:59:23 +1000 Message-Id: <20170605225924.11416-7-benh@kernel.crashing.org> X-Mailer: git-send-email 2.9.4 In-Reply-To: <20170605225924.11416-1-benh@kernel.crashing.org> References: <20170605225924.11416-1-benh@kernel.crashing.org> Subject: [Skiboot] [PATCH 7/8] phb4: Block D-state power management on direct slots X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" As current revisions of PHB4 don't properly handle the resulting L1 link transition. Signed-off-by: Benjamin Herrenschmidt --- core/pci.c | 10 ++++++++++ hw/phb4.c | 34 ++++++++++++++++++++++++++++++---- include/pci-cfg.h | 3 +++ 3 files changed, 43 insertions(+), 4 deletions(-) diff --git a/core/pci.c b/core/pci.c index c791ebd..1477358 100644 --- a/core/pci.c +++ b/core/pci.c @@ -202,11 +202,21 @@ static void pci_init_aer_cap(struct phb *phb, struct pci_device *pd) pci_set_cap(pd, PCIECAP_ID_AER, pos, NULL, true); } +static void pci_init_pm_cap(struct phb *phb, struct pci_device *pd) +{ + int64_t pos; + + pos = pci_find_cap(phb, pd->bdfn, PCI_CFG_CAP_ID_PM); + if (pos > 0) + pci_set_cap(pd, PCI_CFG_CAP_ID_PM, pos, NULL, false); +} + void pci_init_capabilities(struct phb *phb, struct pci_device *pd) { pci_init_pcie_cap(phb, pd); pci_init_aer_cap(phb, pd); pci_init_iov_cap(phb, pd); + pci_init_pm_cap(phb, pd); } static struct pci_device *pci_scan_one(struct phb *phb, struct pci_device *parent, diff --git a/hw/phb4.c b/hw/phb4.c index bf664af..b53dadf 100644 --- a/hw/phb4.c +++ b/hw/phb4.c @@ -644,9 +644,36 @@ static void phb4_endpoint_init(struct phb *phb, pci_cfg_write32(phb, bdfn, aercap + PCIECAP_AER_CAPCTL, val32); } +static int64_t phb4_pcicfg_no_dstate(void *dev, + struct pci_cfg_reg_filter *pcrf, + uint32_t offset, uint32_t len, + uint32_t *data, bool write) +{ + uint32_t loff = offset - pcrf->start; + + /* Disable D-state change on children of the PHB. For now we + * simply block all writes to the PM control/status + */ + if (write && loff >= 4 && loff < 6) + return OPAL_SUCCESS; + + return OPAL_PARTIAL; +} + static void phb4_check_device_quirks(struct phb *phb, struct pci_device *dev) { - // FIXME: add quirks later if necessary + /* Some special adapter tweaks for devices directly under the PHB */ + if (dev->primary_bus != 1) + return; + + /* PM quirk */ + if (!pci_has_cap(dev, PCI_CFG_CAP_ID_PM, false)) + return; + + pci_add_cfg_reg_filter(dev, + pci_cap(dev, PCI_CFG_CAP_ID_PM, false), 8, + PCI_REG_FLAG_WRITE, + phb4_pcicfg_no_dstate); } static int phb4_device_init(struct phb *phb, struct pci_device *dev, @@ -654,9 +681,8 @@ static int phb4_device_init(struct phb *phb, struct pci_device *dev, { int ecap, aercap; - /* Some special adapter tweaks for devices directly under the PHB */ - if (dev->primary_bus == 1) - phb4_check_device_quirks(phb, dev); + /* Setup special device quirks */ + phb4_check_device_quirks(phb, dev); /* Common initialization for the device */ pci_device_init(phb, dev); diff --git a/include/pci-cfg.h b/include/pci-cfg.h index 530f0a8..6061584 100644 --- a/include/pci-cfg.h +++ b/include/pci-cfg.h @@ -108,6 +108,9 @@ #define PCI_CFG_CAP_ID 0 #define PCI_CFG_CAP_NEXT 1 +/* PCI Power Management capability */ +#define PCI_CFG_CAP_ID_PM 1 + /* PCI bridge subsystem ID capability */ #define PCI_CFG_CAP_ID_SUBSYS_VID 0x0d #define PCICAP_SUBSYS_VID_VENDOR 4