From patchwork Mon Jun 5 22:59:19 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Benjamin Herrenschmidt X-Patchwork-Id: 771501 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [103.22.144.68]) (using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3whVfr6jVbz9s5L for ; Tue, 6 Jun 2017 09:01:08 +1000 (AEST) Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 3whVfr5kcGzDqL0 for ; Tue, 6 Jun 2017 09:01:08 +1000 (AEST) X-Original-To: skiboot@lists.ozlabs.org Delivered-To: skiboot@lists.ozlabs.org Received: from gate.crashing.org (gate.crashing.org [63.228.1.57]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 3whVfn5RVMzDqFR for ; Tue, 6 Jun 2017 09:01:05 +1000 (AEST) Received: from pasglop.au.ibm.com (localhost.localdomain [127.0.0.1]) by gate.crashing.org (8.14.1/8.13.8) with ESMTP id v55MxVn3025839; Mon, 5 Jun 2017 17:59:38 -0500 From: Benjamin Herrenschmidt To: skiboot@lists.ozlabs.org Date: Tue, 6 Jun 2017 08:59:19 +1000 Message-Id: <20170605225924.11416-3-benh@kernel.crashing.org> X-Mailer: git-send-email 2.9.4 In-Reply-To: <20170605225924.11416-1-benh@kernel.crashing.org> References: <20170605225924.11416-1-benh@kernel.crashing.org> Subject: [Skiboot] [PATCH 3/8] phb3: Turn the link speed hack into a cfg filter X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" Rather than special casing it openly. Signed-off-by: Benjamin Herrenschmidt --- hw/phb3.c | 35 +++++++++++++++++++++++++---------- 1 file changed, 25 insertions(+), 10 deletions(-) diff --git a/hw/phb3.c b/hw/phb3.c index f32142e..e761cfe 100644 --- a/hw/phb3.c +++ b/hw/phb3.c @@ -216,26 +216,36 @@ static void phb3_link_update(struct phb *phb, uint16_t data) } } -static int64_t phb3_pcicfg_filter(struct phb *phb, uint32_t bdfn, - uint32_t offset, uint32_t len, - uint32_t *data, bool write) +static int64_t phb3_pcicfg_rc_link_speed(void *dev, + struct pci_cfg_reg_filter *pcrf __unused, + uint32_t offset, uint32_t len, + uint32_t *data, bool write) { - struct pci_device *pd; - struct pci_cfg_reg_filter *pcrf; - uint32_t flags; + struct pci_device *pd = dev; /* Hack for link speed changes. We intercept attempts at writing * the link control/status register */ - if (bdfn == 0 && write && len == 4 && offset == 0x58) { - phb3_link_update(phb, (*data) >> 16); + if (write && len == 4 && offset == 0x58) { + phb3_link_update(pd->phb, (*data) >> 16); return OPAL_SUCCESS; } - if (bdfn == 0 && write && len == 2 && offset == 0x5a) { - phb3_link_update(phb, *(uint16_t *)data); + if (write && len == 2 && offset == 0x5a) { + phb3_link_update(pd->phb, *(uint16_t *)data); return OPAL_SUCCESS; } + return OPAL_PARTIAL; +} + +static int64_t phb3_pcicfg_filter(struct phb *phb, uint32_t bdfn, + uint32_t offset, uint32_t len, + uint32_t *data, bool write) +{ + struct pci_device *pd; + struct pci_cfg_reg_filter *pcrf; + uint32_t flags; + if (!pci_device_has_cfg_reg_filters(phb, bdfn)) return OPAL_PARTIAL; pd = pci_find_dev(phb, bdfn); @@ -636,6 +646,11 @@ static void phb3_check_device_quirks(struct phb *phb, struct pci_device *dev) PCI_CFG_PREF_MEM_BASE_U32, 12, PCI_REG_FLAG_READ | PCI_REG_FLAG_WRITE, phb3_pcicfg_rc_pref_window); + /* Add filter to control link speed */ + pci_add_cfg_reg_filter(dev, + 0x58, 4, + PCI_REG_FLAG_WRITE, + phb3_pcicfg_rc_link_speed); } } }