From patchwork Wed May 10 07:09:16 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Russell Currey X-Patchwork-Id: 760439 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) (using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3wN6n60rkHz9rxw for ; Wed, 10 May 2017 17:09:46 +1000 (AEST) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=messagingengine.com header.i=@messagingengine.com header.b="oU+myVu9"; dkim-atps=neutral Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 3wN6n56l6rzDqLS for ; Wed, 10 May 2017 17:09:45 +1000 (AEST) Authentication-Results: lists.ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=messagingengine.com header.i=@messagingengine.com header.b="oU+myVu9"; dkim-atps=neutral X-Original-To: skiboot@lists.ozlabs.org Delivered-To: skiboot@lists.ozlabs.org Received: from out4-smtp.messagingengine.com (out4-smtp.messagingengine.com [66.111.4.28]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 3wN6my6hgszDqKq for ; Wed, 10 May 2017 17:09:38 +1000 (AEST) Authentication-Results: lists.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=messagingengine.com header.i=@messagingengine.com header.b="oU+myVu9"; dkim-atps=neutral Received: from compute6.internal (compute6.nyi.internal [10.202.2.46]) by mailout.nyi.internal (Postfix) with ESMTP id 4609F206DA; Wed, 10 May 2017 03:09:34 -0400 (EDT) Received: from frontend1 ([10.202.2.160]) by compute6.internal (MEProxy); Wed, 10 May 2017 03:09:34 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:date:from:message-id:subject:to :x-me-sender:x-me-sender:x-sasl-enc:x-sasl-enc; s=fm1; bh=gvL/3R OkBj0WDuviOIoHVaQO7uwC0MK7whKitSCKT1s=; b=oU+myVu9UfoQRYWuQIUfSP ELfI3VA3KMQamaO2ez4vto8cNwGWBNkTUSexvFN0M6tEIMd/HQyQR+UU+VDLopYc sEMlsXdBAoLchtAOqwScf06zCuIHN+sShF2xDnmAdipBi7RNXCHMCqVBqHl31IE8 ehFwCezVeIAy1Or8eGYAT8qLkgeVCvrpZM5ZYeaa807kQoBpfIad6CO03jOUqjQ6 ZBW4Ppf9cXgqtSUnw2I6gTc6VeBeh/EFF/36G7TwzgHOqADPJPpyNg4MoW3RdoOa DvoPdeVbyP6/1WhksL34qNEuTSLRlwVEilkCVgdPQo56jcEPThUlRI5AHlTn1ENg == X-ME-Sender: X-Sasl-enc: iuMNAmDGb++5RghSRCr4nh5K6H1aZUc/0c8CZx08WNmX 1494400173 Received: from snap.ozlabs.ibm.com (unknown [122.99.82.10]) by mail.messagingengine.com (Postfix) with ESMTPA id 2A7F67E5C8; Wed, 10 May 2017 03:09:32 -0400 (EDT) From: Russell Currey To: skiboot@lists.ozlabs.org Date: Wed, 10 May 2017 17:09:16 +1000 Message-Id: <20170510070916.3461-1-ruscur@russell.cc> X-Mailer: git-send-email 2.12.2 Subject: [Skiboot] [PATCH v2] phb4: Add an option for disabling EEH MMIO in nvram X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" Having the option to disable EEH for MMIO without rebuilding skiboot could be useful for testing, so check for pci-eeh-mmio=disabled in nvram. Signed-off-by: Russell Currey --- V2: Change to pci-eeh-mmio=disabled thanks to bikeshedding --- hw/phb4.c | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-) diff --git a/hw/phb4.c b/hw/phb4.c index 41468c98..5568b201 100644 --- a/hw/phb4.c +++ b/hw/phb4.c @@ -54,6 +54,7 @@ #include #include #include +#include /* Enable this to disable error interrupts for debug purposes */ #define DISABLE_ERR_INTS @@ -2844,9 +2845,13 @@ static void phb4_init_hw(struct phb4 *p, bool first_init) out_be64(p->regs + PHB_PCIE_CRESET, creset); /* Init_16 - PHB Control */ - out_be64(p->regs + PHB_CTRLR, - PHB_CTRLR_IRQ_PGSZ_64K | - SETFIELD(PHB_CTRLR_TVT_ADDR_SEL, 0ull, TVT_2_PER_PE)); + val = PHB_CTRLR_IRQ_PGSZ_64K | + SETFIELD(PHB_CTRLR_TVT_ADDR_SEL, 0ull, TVT_2_PER_PE); + + if (nvram_query_eq("pci-eeh-mmio", "disabled")) + val |= PHB_CTRLR_MMIO_EEH_DISABLE; + + out_be64(p->regs + PHB_CTRLR, val); /* Init_17..40 - Architected IODA3 inits */ phb4_init_ioda3(p);