diff mbox

[v2] phb4: Add an option for disabling EEH MMIO in nvram

Message ID 20170510070916.3461-1-ruscur@russell.cc
State Accepted
Headers show

Commit Message

Russell Currey May 10, 2017, 7:09 a.m. UTC 
Having the option to disable EEH for MMIO without rebuilding skiboot
could be useful for testing, so check for pci-eeh-mmio=disabled in nvram.

Signed-off-by: Russell Currey <ruscur@russell.cc>
---
V2: Change to pci-eeh-mmio=disabled thanks to bikeshedding
---
 hw/phb4.c | 11 ++++++++---
 1 file changed, 8 insertions(+), 3 deletions(-)

Comments

Stewart Smith May 16, 2017, 5:34 a.m. UTC | #1 
Russell Currey <ruscur@russell.cc> writes:
> Having the option to disable EEH for MMIO without rebuilding skiboot
> could be useful for testing, so check for pci-eeh-mmio=disabled in nvram.
>
> Signed-off-by: Russell Currey <ruscur@russell.cc>
> ---
> V2: Change to pci-eeh-mmio=disabled thanks to bikeshedding

cheers, merged to master as of 85fecf598072cdae850f1eda1f7f2a56882bb68d.
diff mbox

Patch

diff --git a/hw/phb4.c b/hw/phb4.c
index 41468c98..5568b201 100644
--- a/hw/phb4.c
+++ b/hw/phb4.c
@@ -54,6 +54,7 @@ 
 #include <chiptod.h>
 #include <xive.h>
 #include <xscom-p9-regs.h>
+#include <nvram.h>
 
 /* Enable this to disable error interrupts for debug purposes */
 #define DISABLE_ERR_INTS
@@ -2844,9 +2845,13 @@  static void phb4_init_hw(struct phb4 *p, bool first_init)
 	out_be64(p->regs + PHB_PCIE_CRESET,			   creset);
 
 	/* Init_16 - PHB Control */
-	out_be64(p->regs + PHB_CTRLR,
-		 PHB_CTRLR_IRQ_PGSZ_64K |
-		 SETFIELD(PHB_CTRLR_TVT_ADDR_SEL, 0ull, TVT_2_PER_PE));
+	val = PHB_CTRLR_IRQ_PGSZ_64K |
+		SETFIELD(PHB_CTRLR_TVT_ADDR_SEL, 0ull, TVT_2_PER_PE);
+
+	if (nvram_query_eq("pci-eeh-mmio", "disabled"))
+		val |= PHB_CTRLR_MMIO_EEH_DISABLE;
+
+	out_be64(p->regs + PHB_CTRLR, val);
 
 	/* Init_17..40 - Architected IODA3 inits */
 	phb4_init_ioda3(p);