From patchwork Sat Mar 11 06:18:26 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Benjamin Herrenschmidt X-Patchwork-Id: 737642 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [103.22.144.68]) (using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3vgDZM0qmfz9s7v for ; Sat, 11 Mar 2017 17:22:35 +1100 (AEDT) Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 3vgDZL6vbLzDqYQ for ; Sat, 11 Mar 2017 17:22:34 +1100 (AEDT) X-Original-To: skiboot@lists.ozlabs.org Delivered-To: skiboot@lists.ozlabs.org Received: from gate.crashing.org (gate.crashing.org [63.228.1.57]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 3vgDZ75W2tzDqXf for ; Sat, 11 Mar 2017 17:22:23 +1100 (AEDT) Received: from pasglop.au.ibm.com (localhost.localdomain [127.0.0.1]) by gate.crashing.org (8.14.1/8.13.8) with ESMTP id v2B6Ic0b019476; Sat, 11 Mar 2017 00:18:39 -0600 From: Benjamin Herrenschmidt To: skiboot@lists.ozlabs.org Date: Sat, 11 Mar 2017 17:18:26 +1100 Message-Id: <20170311061826.9974-1-benh@kernel.crashing.org> X-Mailer: git-send-email 2.9.3 Subject: [Skiboot] [PATCH] xive: Don't mess around with the ESB state when setting an IRQ config X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" The host code needs to manage the ESB state in specific ways, it's not correct to blindly unmask the source when targetting for example, so let's not do that, the host will do it itself when appropriate. Signed-off-by: Benjamin Herrenschmidt --- hw/xive.c | 14 ++++++++++---- 1 file changed, 10 insertions(+), 4 deletions(-) diff --git a/hw/xive.c b/hw/xive.c index 43eda30..9ccf7e7 100644 --- a/hw/xive.c +++ b/hw/xive.c @@ -3403,7 +3403,16 @@ static int64_t opal_xive_set_irq_config(uint32_t girq, int64_t rc; /* - * WARNING: See comment in set_xive() + * This variant is meant for a XIVE-aware OS, thus it will + * *not* affect the ESB state of the interrupt. If used with + * a prio of FF, the IVT/EAS will be mased. In that case the + * races have to be handled by the OS. + * + * The exception to this rule is interrupts for which masking + * and unmasking is handled by firmware. In that case the ESB + * state isn't under OS control and will be dealt here. This + * is currently only the case of LSIs and on P9 DD1.0 only so + * isn't an issue. */ if (xive_mode != XIVE_MODE_EXPL) @@ -3427,9 +3436,6 @@ static int64_t opal_xive_set_irq_config(uint32_t girq, * is handled by the XIVE */ rc = s->orig_ops->set_xive(is, girq, 0, prio); - } else { - /* Ensure it's enabled/disabled in the source controller */ - xive_update_irq_mask(s, girq - s->esb_base, prio == 0xff); } /*