From patchwork Tue Oct 11 05:04:07 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Russell Currey X-Patchwork-Id: 680608 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [103.22.144.68]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3stPzw6Cnnz9sBR for ; Tue, 11 Oct 2016 16:04:28 +1100 (AEDT) Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 3stPzw5QFMzDskm for ; Tue, 11 Oct 2016 16:04:28 +1100 (AEDT) X-Original-To: skiboot@lists.ozlabs.org Delivered-To: skiboot@lists.ozlabs.org Received: from russell.cc (russell.cc [43.229.61.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 3stPzs3KX8zDrSF for ; Tue, 11 Oct 2016 16:04:25 +1100 (AEDT) Received: from snap.ozlabs.ibm.com (static-82-10.transact.net.au [122.99.82.10]) by russell.cc (OpenSMTPD) with ESMTPSA id 3925db25 (TLSv1.2:ECDHE-RSA-AES128-GCM-SHA256:128:NO); Tue, 11 Oct 2016 05:04:17 +0000 (UTC) From: Russell Currey To: skiboot@lists.ozlabs.org Date: Tue, 11 Oct 2016 16:04:07 +1100 Message-Id: <20161011050407.24178-1-ruscur@russell.cc> X-Mailer: git-send-email 2.10.0 Subject: [Skiboot] [PATCH v2] pci: Avoid hot reset after post-fundamental reset X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" In the PCI post-fundamental reset code, a hot reset is performed at the end. This is causing issues at boot time as a reset signal is being sent downstream before the links are up, which is causing issues on adapters behind switches. No errors result in skiboot, but the adapters are not usable in Linux as a result. This patch fixes some adapters not being configurable in Linux on some systems. The issue was not present in skiboot 5.2.x. Cc: stable # 5.3.x Signed-off-by: Russell Currey Acked-by: Gavin Shan --- hw/p7ioc-phb.c | 4 ++-- hw/phb3.c | 4 ++-- hw/phb4.c | 8 -------- 3 files changed, 4 insertions(+), 12 deletions(-) diff --git a/hw/p7ioc-phb.c b/hw/p7ioc-phb.c index d2a18a3..1f1b362 100644 --- a/hw/p7ioc-phb.c +++ b/hw/p7ioc-phb.c @@ -2234,8 +2234,8 @@ static int64_t p7ioc_freset(struct pci_slot *slot) return slot->ops.pfreset(slot); } - pci_slot_set_state(slot, P7IOC_SLOT_HRESET_START); - return slot->ops.hreset(slot); + pci_slot_set_state(slot, P7IOC_SLOT_LINK_START); + return slot->ops.poll_link(slot); default: PHBERR(p, "FRESET: Unexpected slot state %08x\n", slot->state); diff --git a/hw/phb3.c b/hw/phb3.c index d0b5010..817137b 100644 --- a/hw/phb3.c +++ b/hw/phb3.c @@ -2240,8 +2240,8 @@ static int64_t phb3_pfreset(struct pci_slot *slot) /* CAPP FPGA requires 1s to flash before polling link */ return pci_slot_set_sm_timeout(slot, secs_to_tb(1)); case PHB3_SLOT_PFRESET_DEASSERT_DELAY: - pci_slot_set_state(slot, PHB3_SLOT_HRESET_START); - return slot->ops.hreset(slot); + pci_slot_set_state(slot, PHB3_SLOT_LINK_START); + return slot->ops.poll_link(slot); default: PHBERR(p, "Unexpected slot state %08x\n", slot->state); } diff --git a/hw/phb4.c b/hw/phb4.c index 385ce8c..efb6a5f 100644 --- a/hw/phb4.c +++ b/hw/phb4.c @@ -1951,16 +1951,8 @@ static int64_t phb4_pfreset(struct pci_slot *slot) /* CAPP FPGA requires 1s to flash before polling link */ return pci_slot_set_sm_timeout(slot, secs_to_tb(1)); case PHB4_SLOT_PFRESET_DEASSERT_DELAY: -#if 0 /* PHB3 does a Hreset here. It's unnecessary I think and it's - * causing problems with the simulator croc model so don't do - * it until I figure out Gavin's reasons - */ - pci_slot_set_state(slot, PHB4_SLOT_HRESET_START); - return slot->ops.hreset(slot); -#else pci_slot_set_state(slot, PHB4_SLOT_LINK_START); return slot->ops.poll_link(slot); -#endif default: PHBERR(p, "Unexpected slot state %08x\n", slot->state); }