From patchwork Tue Sep 27 00:51:52 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Russell Currey X-Patchwork-Id: 675353 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [103.22.144.68]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3sjj3C6Swwz9s4n for ; Tue, 27 Sep 2016 10:52:07 +1000 (AEST) Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 3sjj3C5fL8zDrTM for ; Tue, 27 Sep 2016 10:52:07 +1000 (AEST) X-Original-To: skiboot@lists.ozlabs.org Delivered-To: skiboot@lists.ozlabs.org Received: from russell.cc (russell.cc [IPv6:2404:9400:2:0:216:3eff:fee0:3370]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 3sjj334W99zDrSK for ; Tue, 27 Sep 2016 10:51:59 +1000 (AEST) Received: from snap.ozlabs.ibm.com (static-82-10.transact.net.au [122.99.82.10]) by russell.cc (OpenSMTPD) with ESMTPSA id 92bccb65 (TLSv1.2:ECDHE-RSA-AES128-GCM-SHA256:128:NO); Tue, 27 Sep 2016 00:52:02 +0000 (UTC) From: Russell Currey To: skiboot@lists.ozlabs.org Date: Tue, 27 Sep 2016 10:51:52 +1000 Message-Id: <20160927005152.17676-1-ruscur@russell.cc> X-Mailer: git-send-email 2.10.0 Subject: [Skiboot] [PATCH] phb3/4: Don't perform a hot reset at boot X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: stable#5.3.x@russell.cc MIME-Version: 1.0 Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" Recent releases of skiboot contain a regression, causing certain adapters behind certain switches to timeout waiting for links to come up. This is due to a hot reset at boot time: a) having to permeate down through all devices and b) being potentially unsafe given the links aren't up yet. Avoid the hot reset at boot in phb3 and phb4. Cc: stable # 5.3.x Signed-off-by: Russell Currey --- hw/phb3.c | 2 +- hw/phb4.c | 10 +--------- 2 files changed, 2 insertions(+), 10 deletions(-) diff --git a/hw/phb3.c b/hw/phb3.c index d0b5010..b8e3439 100644 --- a/hw/phb3.c +++ b/hw/phb3.c @@ -2240,7 +2240,7 @@ static int64_t phb3_pfreset(struct pci_slot *slot) /* CAPP FPGA requires 1s to flash before polling link */ return pci_slot_set_sm_timeout(slot, secs_to_tb(1)); case PHB3_SLOT_PFRESET_DEASSERT_DELAY: - pci_slot_set_state(slot, PHB3_SLOT_HRESET_START); + pci_slot_set_state(slot, PHB3_SLOT_HRESET_DELAY); return slot->ops.hreset(slot); default: PHBERR(p, "Unexpected slot state %08x\n", slot->state); diff --git a/hw/phb4.c b/hw/phb4.c index 385ce8c..746bfb7 100644 --- a/hw/phb4.c +++ b/hw/phb4.c @@ -1951,16 +1951,8 @@ static int64_t phb4_pfreset(struct pci_slot *slot) /* CAPP FPGA requires 1s to flash before polling link */ return pci_slot_set_sm_timeout(slot, secs_to_tb(1)); case PHB4_SLOT_PFRESET_DEASSERT_DELAY: -#if 0 /* PHB3 does a Hreset here. It's unnecessary I think and it's - * causing problems with the simulator croc model so don't do - * it until I figure out Gavin's reasons - */ - pci_slot_set_state(slot, PHB4_SLOT_HRESET_START); + pci_slot_set_state(slot, PHB4_SLOT_HRESET_DELAY); return slot->ops.hreset(slot); -#else - pci_slot_set_state(slot, PHB4_SLOT_LINK_START); - return slot->ops.poll_link(slot); -#endif default: PHBERR(p, "Unexpected slot state %08x\n", slot->state); }