From patchwork Tue Jun 21 08:04:47 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Russell Currey X-Patchwork-Id: 638549 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3rYgJ12yV1z9sBg for ; Tue, 21 Jun 2016 18:05:05 +1000 (AEST) Received: from ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 3rYgJ129fbzDqCY for ; Tue, 21 Jun 2016 18:05:05 +1000 (AEST) X-Original-To: skiboot@lists.ozlabs.org Delivered-To: skiboot@lists.ozlabs.org Received: from russell.cc (russell.cc [IPv6:2404:9400:2:0:216:3eff:fee0:3370]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 3rYgHx2YNzzDq5c for ; Tue, 21 Jun 2016 18:05:01 +1000 (AEST) Received: from snap.ozlabs.ibm.com (static-82-10.transact.net.au [122.99.82.10]) by russell.cc (OpenSMTPD) with ESMTPSA id 8fc031d8 TLS version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128 verify=NO; Tue, 21 Jun 2016 08:05:01 +0000 (UTC) From: Russell Currey To: skiboot@lists.ozlabs.org Date: Tue, 21 Jun 2016 18:04:47 +1000 Message-Id: <20160621080448.25155-1-ruscur@russell.cc> X-Mailer: git-send-email 2.9.0 Subject: [Skiboot] [PATCH v2 1/2] astbmc: Add NPU slot type and use it in Garrison X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair@popple.id.au MIME-Version: 1.0 Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" NPU links are grouped into pairs, signifying that they both correlate to the same physical GPU. These pairs are presented in the Garrison slot table as typical PCI devices, creating what are essentially redundant entries. Add a new slot type specifically for NPUs, and subsequently perform bdfn correlation using it. Signed-off-by: Russell Currey --- V2: New change to facilitate bdfn allocation without using pbcq --- platforms/astbmc/astbmc.h | 2 ++ platforms/astbmc/garrison.c | 36 ++++++++---------------------------- platforms/astbmc/slots.c | 7 +++++++ 3 files changed, 17 insertions(+), 28 deletions(-) diff --git a/platforms/astbmc/astbmc.h b/platforms/astbmc/astbmc.h index 23c31c7..0cf2ac1 100644 --- a/platforms/astbmc/astbmc.h +++ b/platforms/astbmc/astbmc.h @@ -20,6 +20,7 @@ #define ST_LOC_PHB(chip_id, phb_idx) ((chip_id) << 16 | (phb_idx)) #define ST_LOC_DEVFN(dev, fn) ((dev) << 3 | (fn)) +#define ST_LOC_NPU_GROUP(group_id) (group_id) struct slot_table_entry { enum slot_table_etype { @@ -27,6 +28,7 @@ struct slot_table_entry { st_phb, st_pluggable_slot, st_builtin_dev, + st_npu_slot } etype; uint32_t location; const char *name; diff --git a/platforms/astbmc/garrison.c b/platforms/astbmc/garrison.c index 3ff84a3..fb006db 100644 --- a/platforms/astbmc/garrison.c +++ b/platforms/astbmc/garrison.c @@ -63,23 +63,13 @@ static const struct slot_table_entry garrison_phb0_3_slot[] = { static const struct slot_table_entry garrison_npu0_slots[] = { { - .etype = st_pluggable_slot, - .location = ST_LOC_DEVFN(0,0), - .name = "GPU2", - }, - { - .etype = st_pluggable_slot, - .location = ST_LOC_DEVFN(0,1), + .etype = st_npu_slot, + .location = ST_LOC_NPU_GROUP(0), .name = "GPU2", }, { - .etype = st_pluggable_slot, - .location = ST_LOC_DEVFN(1,0), - .name = "GPU1", - }, - { - .etype = st_pluggable_slot, - .location = ST_LOC_DEVFN(1,1), + .etype = st_npu_slot, + .location = ST_LOC_NPU_GROUP(1), .name = "GPU1", }, { .etype = st_end }, @@ -152,23 +142,13 @@ static const struct slot_table_entry garrison_phb1_3_slot[] = { static const struct slot_table_entry garrison_npu1_slots[] = { { - .etype = st_pluggable_slot, - .location = ST_LOC_DEVFN(0,0), - .name = "GPU4", - }, - { - .etype = st_pluggable_slot, - .location = ST_LOC_DEVFN(0,1), + .etype = st_npu_slot, + .location = ST_LOC_NPU_GROUP(0), .name = "GPU4", }, { - .etype = st_pluggable_slot, - .location = ST_LOC_DEVFN(1,0), - .name = "GPU3", - }, - { - .etype = st_pluggable_slot, - .location = ST_LOC_DEVFN(1,1), + .etype = st_npu_slot, + .location = ST_LOC_NPU_GROUP(1), .name = "GPU3", }, { .etype = st_end }, diff --git a/platforms/astbmc/slots.c b/platforms/astbmc/slots.c index 36547e1..992f68b 100644 --- a/platforms/astbmc/slots.c +++ b/platforms/astbmc/slots.c @@ -70,6 +70,13 @@ static const struct slot_table_entry *match_slot_dev_entry(struct phb *phb, prerror("SLOT: Bad PHB entry type in table !\n"); continue; } + + if (ent->etype == st_npu_slot) { + /* NPU groups are at device level, so ignore function */ + if (ent->location == ((pd->bdfn & 0xff) >> 3)) + return ent; + } + if (ent->location == (pd->bdfn & 0xff)) return ent; }