From patchwork Mon Jun 20 06:40:48 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Russell Currey X-Patchwork-Id: 637834 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3rY1Tk55fdz9sDG for ; Mon, 20 Jun 2016 16:41:14 +1000 (AEST) Received: from ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 3rY1Tk4FPyzDqCv for ; Mon, 20 Jun 2016 16:41:14 +1000 (AEST) X-Original-To: skiboot@lists.ozlabs.org Delivered-To: skiboot@lists.ozlabs.org Received: from russell.cc (russell.cc [IPv6:2404:9400:2:0:216:3eff:fee0:3370]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 3rY1TQ5M9VzDq5d for ; Mon, 20 Jun 2016 16:40:58 +1000 (AEST) Received: from snap.ozlabs.ibm.com (static-82-10.transact.net.au [122.99.82.10]) by russell.cc (OpenSMTPD) with ESMTPSA id 3a90aa05 TLS version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128 verify=NO; Mon, 20 Jun 2016 06:40:58 +0000 (UTC) From: Russell Currey To: skiboot@lists.ozlabs.org Date: Mon, 20 Jun 2016 16:40:48 +1000 Message-Id: <20160620064048.19333-1-ruscur@russell.cc> X-Mailer: git-send-email 2.9.0 Subject: [Skiboot] [PATCH] nvlink: Enable NPU device BAR before triggering freeze X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair@popple.id.au MIME-Version: 1.0 Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" NPU freeze injection works by performing an invalid MMIO read on the NPU device BAR. If the BAR isn't enabled, which is the case when the appropriate driver isn't loaded, this checkstops the machine. Work around this by making sure the BAR is enabled before performing the read. The idea of an error inject doing anything other than an error inject isn't great, but it's better than unintentionally crashing your machine. Also, fix the comment incorrectly stating the operation was a write instead of a read. Signed-off-by: Russell Currey --- hw/npu.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/hw/npu.c b/hw/npu.c index e444b96..834b3e3 100644 --- a/hw/npu.c +++ b/hw/npu.c @@ -1118,7 +1118,10 @@ static int64_t npu_err_inject(struct phb *phb, uint32_t pe_num, /* Emulate fence mode. */ p->fenced = true; } else { - /* Cause a freeze with an invalid MMIO write. */ + /* Cause a freeze with an invalid MMIO read. If the BAR is not + * enabled, this will checkstop the machine. + */ + npu_dev_bar_update(p->chip_id, &dev->bar, true); in_be64((void *)dev->bar.base); }