From patchwork Thu Jun 16 01:24:41 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Russell Currey X-Patchwork-Id: 636154 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [103.22.144.68]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3rVQfj20JBz9s6r for ; Thu, 16 Jun 2016 11:25:01 +1000 (AEST) Received: from ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 3rVQfj1Dx0zDqmr for ; Thu, 16 Jun 2016 11:25:01 +1000 (AEST) X-Original-To: skiboot@lists.ozlabs.org Delivered-To: skiboot@lists.ozlabs.org Received: from russell.cc (russell.cc [IPv6:2404:9400:2:0:216:3eff:fee0:3370]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 3rVQfW4dFmzDqln for ; Thu, 16 Jun 2016 11:24:51 +1000 (AEST) Received: from snap.ozlabs.ibm.com (static-82-10.transact.net.au [122.99.82.10]) by russell.cc (OpenSMTPD) with ESMTPSA id 34911e28 TLS version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128 verify=NO; Thu, 16 Jun 2016 01:24:49 +0000 (UTC) From: Russell Currey To: skiboot@lists.ozlabs.org Date: Thu, 16 Jun 2016 11:24:41 +1000 Message-Id: <20160616012441.13118-1-ruscur@russell.cc> X-Mailer: git-send-email 2.8.3 Subject: [Skiboot] [PATCH] nvlink: Present chip ID as the NPU PHB slot location X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair@popple.id.au MIME-Version: 1.0 Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" EEH errors in the kernel report the physical slot location of the erroneous PE and its PHB. For NPU devices, the PE's slot location will refer to the physical GPU the link is associated with, and the PHB is actually a NPU chip which has no relevance to a physical slot on a board. Rather than reporting N/A for a NPU PHB's slot location, present the chip number. It's not particularly useful, but better than nothing. Signed-off-by: Russell Currey --- hw/npu.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/hw/npu.c b/hw/npu.c index c371f4c..b99a2e5 100644 --- a/hw/npu.c +++ b/hw/npu.c @@ -1710,6 +1710,7 @@ static void npu_add_phb_properties(struct npu *p) 0x800, 0x0, 0x0, 0x1, icsp, base_lsi + 2, 0x800, 0x0, 0x0, 0x2, icsp, base_lsi + 3 }; uint32_t mask[] = {0xf800, 0x0, 0x0, 0x7}; + char slotbuf[32]; /* Add various properties that HB doesn't have to * add, some of them simply because they result from @@ -1764,6 +1765,13 @@ static void npu_add_phb_properties(struct npu *p) hi32(mm_base), lo32(mm_base), hi32(mm_base), lo32(mm_base), hi32(mm_size), lo32(mm_size)); + + /* Set the slot location on the NPU PHB. This PHB can contain + * devices that correlate with multiple physical slots, so + * present the chip ID instead. + */ + snprintf(slotbuf, sizeof(slotbuf), "NPU Chip %d", p->chip_id); + dt_add_property_string(np, "ibm,io-base-loc-code", slotbuf); } static void npu_create_phb(struct dt_node *dn)