From patchwork Thu Feb 5 05:58:54 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mahesh J Salgaonkar X-Patchwork-Id: 436626 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 19E921400A0 for ; Thu, 5 Feb 2015 16:59:06 +1100 (AEDT) Received: from ozlabs.org (ozlabs.org [103.22.144.67]) by lists.ozlabs.org (Postfix) with ESMTP id 09F2D1A0A1C for ; Thu, 5 Feb 2015 16:59:06 +1100 (AEDT) X-Original-To: skiboot@lists.ozlabs.org Delivered-To: skiboot@lists.ozlabs.org Received: from e28smtp09.in.ibm.com (e28smtp09.in.ibm.com [122.248.162.9]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id DBE431A095B for ; Thu, 5 Feb 2015 16:59:02 +1100 (AEDT) Received: from /spool/local by e28smtp09.in.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! 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Violators will be prosecuted; Thu, 5 Feb 2015 11:28:55 +0530 Received: from d28relay02.in.ibm.com (d28relay02.in.ibm.com [9.184.220.59]) by d28dlp01.in.ibm.com (Postfix) with ESMTP id 0D6A7E005A for ; Thu, 5 Feb 2015 11:30:24 +0530 (IST) Received: from d28av05.in.ibm.com (d28av05.in.ibm.com [9.184.220.67]) by d28relay02.in.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id t155wtw155246972 for ; Thu, 5 Feb 2015 11:28:55 +0530 Received: from d28av05.in.ibm.com (localhost [127.0.0.1]) by d28av05.in.ibm.com (8.14.4/8.14.4/NCO v10.0 AVout) with ESMTP id t155wsQl018134 for ; Thu, 5 Feb 2015 11:28:55 +0530 Received: from [9.109.222.221] (mars.in.ibm.com [9.124.35.30] (may be forged)) by d28av05.in.ibm.com (8.14.4/8.14.4/NCO v10.0 AVin) with ESMTP id t155ws9v018130; Thu, 5 Feb 2015 11:28:54 +0530 From: Mahesh J Salgaonkar To: skiboot list , Benjamin Herrenschmidt Date: Thu, 05 Feb 2015 11:28:54 +0530 Message-ID: <20150205055803.2171.22081.stgit@mars> In-Reply-To: <20150205055223.2171.85573.stgit@mars> References: <20150205055223.2171.85573.stgit@mars> User-Agent: StGit/0.17-dirty MIME-Version: 1.0 X-TM-AS-MML: disable X-Content-Scanned: Fidelis XPS MAILER x-cbid: 15020505-0033-0000-0000-000004351644 Subject: [Skiboot] [PATCH v2 3/3] opal: Check NX FIRs to find the reason for Malfunction Alert. X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" From: Mahesh Salgaonkar On Malfunction Alert check if it has driven by NX. The NX status register HMI Active bit will be set if HMI is caused due to NX checkstop. Read all NX FIRs to identify reason for check stop and update a HMI event with relevant error information. Signed-off-by: Mahesh Salgaonkar --- core/hmi.c | 86 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 86 insertions(+) diff --git a/core/hmi.c b/core/hmi.c index 2a21fee..506bc2c 100644 --- a/core/hmi.c +++ b/core/hmi.c @@ -148,6 +148,15 @@ /* xscom addresses for core FIR (Fault Isolation Register) */ #define CORE_FIR 0x10013100 +#define NX_STATUS_REG 0x02013040 /* NX status register */ +#define NX_DMA_ENGINE_FIR 0x02013100 /* DMA & Engine FIR Data Register */ +#define NX_PBI_FIR 0x02013080 /* PowerBus Interface FIR Register */ + +/* + * Bit 54 from NX status register is set to 1 when HMI interrupt is triggered + * due to NX checksop. + */ +#define NX_HMI_ACTIVE PPC_BIT(54) static const struct core_xstop_bit_info { uint8_t bit; /* CORE FIR bit number */ @@ -172,6 +181,29 @@ static const struct core_xstop_bit_info { { 63, CORE_CHECKSTOP_PC_SPRD_HYP_ERR_INJ }, }; +static const struct nx_xstop_bit_info { + uint8_t bit; /* NX FIR bit number */ + enum OpalHMI_NestAccelXstopReason reason; +} nx_dma_xstop_bits[] = { + { 1, NX_CHECKSTOP_SHM_INVAL_STATE_ERR }, + { 15, NX_CHECKSTOP_DMA_INVAL_STATE_ERR_1 }, + { 16, NX_CHECKSTOP_DMA_INVAL_STATE_ERR_2 }, + { 20, NX_CHECKSTOP_DMA_CH0_INVAL_STATE_ERR }, + { 21, NX_CHECKSTOP_DMA_CH1_INVAL_STATE_ERR }, + { 22, NX_CHECKSTOP_DMA_CH2_INVAL_STATE_ERR }, + { 23, NX_CHECKSTOP_DMA_CH3_INVAL_STATE_ERR }, + { 24, NX_CHECKSTOP_DMA_CH4_INVAL_STATE_ERR }, + { 25, NX_CHECKSTOP_DMA_CH5_INVAL_STATE_ERR }, + { 26, NX_CHECKSTOP_DMA_CH6_INVAL_STATE_ERR }, + { 27, NX_CHECKSTOP_DMA_CH7_INVAL_STATE_ERR }, + { 31, NX_CHECKSTOP_DMA_CRB_UE }, + { 32, NX_CHECKSTOP_DMA_CRB_SUE }, +}; + +static const struct nx_xstop_bit_info nx_pbi_xstop_bits[] = { + { 12, NX_CHECKSTOP_PBI_ISN_UE }, +}; + static struct lock hmi_lock = LOCK_UNLOCKED; static int queue_hmi_event(struct OpalHMIEvent *hmi_evt, int recover) @@ -318,6 +350,58 @@ static void find_core_checkstop_reason(struct OpalHMIEvent *hmi_evt, } } +static void find_nx_checkstop_reason(int flat_chip_id, + struct OpalHMIEvent *hmi_evt, int *event_generated) +{ + uint64_t nx_status; + uint64_t nx_dma_fir; + uint64_t nx_pbi_fir; + int i; + + /* Get NX status register value. */ + if (xscom_read(flat_chip_id, NX_STATUS_REG, &nx_status) != 0) { + prerror("HMI: XSCOM error reading NX_STATUS_REG\n"); + return; + } + + /* Check if NX has driven an HMI interrupt. */ + if (!(nx_status & NX_HMI_ACTIVE)) + return; + + /* Initialize HMI event */ + hmi_evt->severity = OpalHMI_SEV_FATAL; + hmi_evt->type = OpalHMI_ERROR_MALFUNC_ALERT; + hmi_evt->u.xstop_error.xstop_type = CHECKSTOP_TYPE_NX; + hmi_evt->u.xstop_error.u.chip_id = flat_chip_id; + + /* Get DMA & Engine FIR data register value. */ + if (xscom_read(flat_chip_id, NX_DMA_ENGINE_FIR, &nx_dma_fir) != 0) { + prerror("HMI: XSCOM error reading NX_DMA_ENGINE_FIR\n"); + return; + } + + /* Get PowerBus Interface FIR data register value. */ + if (xscom_read(flat_chip_id, NX_PBI_FIR, &nx_pbi_fir) != 0) { + prerror("HMI: XSCOM error reading NX_DMA_ENGINE_FIR\n"); + return; + } + + /* Find NX checkstop reason and populate HMI event with error info. */ + for (i = 0; i < ARRAY_SIZE(nx_dma_xstop_bits); i++) + if (nx_dma_fir & PPC_BIT(nx_dma_xstop_bits[i].bit)) + hmi_evt->u.xstop_error.xstop_reason + |= nx_dma_xstop_bits[i].reason; + + for (i = 0; i < ARRAY_SIZE(nx_pbi_xstop_bits); i++) + if (nx_pbi_fir & PPC_BIT(nx_pbi_xstop_bits[i].bit)) + hmi_evt->u.xstop_error.xstop_reason + |= nx_pbi_xstop_bits[i].reason; + + /* Send an HMI event. */ + queue_hmi_event(hmi_evt, 0); + *event_generated = 1; +} + static int decode_malfunction(struct OpalHMIEvent *hmi_evt) { int i; @@ -335,6 +419,8 @@ static int decode_malfunction(struct OpalHMIEvent *hmi_evt) queue_hmi_event(hmi_evt, recover); event_generated = 1; } + + find_nx_checkstop_reason(i, hmi_evt, &event_generated); } if (recover != -1) {