diff mbox series

[4/4] npu3: Make SALT CMD_REG writable

Message ID 1571779344-28464-5-git-send-email-arbab@linux.ibm.com
State Accepted
Headers show
Series npu3: Bringup errata | expand

Checks

Context Check Description
snowpatch_ozlabs/apply_patch success Successfully applied on branch master (d75e82dbfbb9443efeb3f9a5921ac23605aab469)
snowpatch_ozlabs/snowpatch_job_snowpatch-skiboot success Test snowpatch/job/snowpatch-skiboot on branch master
snowpatch_ozlabs/snowpatch_job_snowpatch-skiboot-dco success Signed-off-by present

Commit Message

Reza Arbab Oct. 22, 2019, 9:22 p.m. UTC 
CMD_REG should be writable, not read-only. Fix this, initializing it
with a default "unset" value (0xffffffff).

Signed-off-by: Reza Arbab <arbab@linux.ibm.com>
---
 hw/npu3-nvlink.c | 7 ++++---
 1 file changed, 4 insertions(+), 3 deletions(-)
diff mbox series

Patch

diff --git a/hw/npu3-nvlink.c b/hw/npu3-nvlink.c
index 3457b7314c35..9630158979c9 100644
--- a/hw/npu3-nvlink.c
+++ b/hw/npu3-nvlink.c
@@ -1218,8 +1218,9 @@  static int64_t npu3_dev_salt(void *pvd, struct pci_cfg_reg_filter *pcrf,
 		return OPAL_PARAMETER;
 
 	/* The config register before this one holds CMD_REG */
-	pci_virt_cfg_read_raw(pvd, PCI_VIRT_CFG_NORMAL, pcrf->start - 4,
-			      4, &cmd_reg);
+	PCI_VIRT_CFG_NORMAL_RD(pvd, pcrf->start - 4, 4, &cmd_reg);
+	if (cmd_reg == 0xffffffff)
+		return OPAL_PARAMETER;
 
 	/* Check for another command in progress */
 	val = npu3_dev_ppe_sram_read(dev, OB_PPE_SALT_CMD);
@@ -1290,7 +1291,7 @@  static uint32_t npu3_cfg_populate_vendor_cap(struct npu3_dev *dev,
 	PCI_VIRT_CFG_INIT_RO(pvd, start + 0xc, 1, npu3_chip_dev_index(dev));
 
 	/* SALT registers */
-	PCI_VIRT_CFG_INIT_RO(pvd, start + 0x10, 4, 0);
+	PCI_VIRT_CFG_INIT(pvd, start + 0x10, 4, 0xffffffff, 0, 0);
 	PCI_VIRT_CFG_INIT_RO(pvd, start + 0x14, 4, 0);
 
 	pci_virt_add_filter(pvd, start + 0x14, 4,