diff mbox series

npu3: Delay enablement of DL parity checking

Message ID 1566335575-23232-1-git-send-email-arbab@linux.ibm.com
State Accepted
Headers show
Series npu3: Delay enablement of DL parity checking | expand

Checks

Context Check Description
snowpatch_ozlabs/apply_patch success Successfully applied on branch master (a1fced25bf41f1f94a3673a0b2bf68135eedce25)
snowpatch_ozlabs/snowpatch_job_snowpatch-skiboot success Test snowpatch/job/snowpatch-skiboot on branch master
snowpatch_ozlabs/snowpatch_job_snowpatch-skiboot-dco success Signed-off-by present

Commit Message

Reza Arbab Aug. 20, 2019, 9:12 p.m. UTC 
Currently, we turn on TX and PRI parity checking of the DL during NPU
initialization, while RX parity checking is not enabled until after link
training.

This behavior was prescribed for npu2, but on npu3 systems the logic has
changed such that we're getting early parity error checkstops.

To fix, only set the TX and PRI enable bits after training, consistent
with RX.

Signed-off-by: Reza Arbab <arbab@linux.ibm.com>
---
 hw/npu3-hw-procedures.c | 12 ++++++++----
 hw/npu3-nvlink.c        |  2 --
 2 files changed, 8 insertions(+), 6 deletions(-)
diff mbox series

Patch

diff --git a/hw/npu3-hw-procedures.c b/hw/npu3-hw-procedures.c
index 54f4b3576880..86067a028d3e 100644
--- a/hw/npu3-hw-procedures.c
+++ b/hw/npu3-hw-procedures.c
@@ -557,9 +557,11 @@  static uint32_t reset_ntl(struct npu3_dev *dev)
 	val = SETFIELD(NPU3_NTL_PRI_CFG_NDL, 0ull, dev->index);
 	npu3_write(npu, NPU3_NTL_PRI_CFG(dev->index), val);
 
-	/* Disable RX parity checking */
+	/* Disable parity checking */
 	val = npu3_read(npu, NPU3_NTL_MISC_CFG2(dev->index));
-	val &= ~NPU3_NTL_MISC_CFG2_NDL_RX_PARITY_ENA;
+	val &= ~(NPU3_NTL_MISC_CFG2_NDL_RX_PARITY_ENA |
+		 NPU3_NTL_MISC_CFG2_NDL_TX_PARITY_ENA |
+		 NPU3_NTL_MISC_CFG2_NDL_PRI_PARITY_ENA);
 	npu3_write(npu, NPU3_NTL_MISC_CFG2(dev->index), val);
 
 	if (dev->type == NPU3_DEV_TYPE_NVLINK)
@@ -636,9 +638,11 @@  static uint32_t reset_ntl_finish(struct npu3_dev *dev) {
 	if (npu3_dev_fence_get(dev) != NPU3_NTL_CQ_FENCE_STATUS_NONE)
 		return NPU3_PROC_INPROGRESS;
 
-	/* Enable RX parity checking */
+	/* Enable parity checking */
 	val = npu3_read(npu, NPU3_NTL_MISC_CFG2(dev->index));
-	val |= NPU3_NTL_MISC_CFG2_NDL_RX_PARITY_ENA;
+	val |= NPU3_NTL_MISC_CFG2_NDL_RX_PARITY_ENA |
+	       NPU3_NTL_MISC_CFG2_NDL_TX_PARITY_ENA |
+	       NPU3_NTL_MISC_CFG2_NDL_PRI_PARITY_ENA;
 	npu3_write(npu, NPU3_NTL_MISC_CFG2(dev->index), val);
 
 	if (dev->type == NPU3_DEV_TYPE_NVLINK)
diff --git a/hw/npu3-nvlink.c b/hw/npu3-nvlink.c
index 35f68a84c1ea..6969b89b2488 100644
--- a/hw/npu3-nvlink.c
+++ b/hw/npu3-nvlink.c
@@ -928,8 +928,6 @@  static void npu3_dev_init_hw(struct npu3_dev *dev)
 	reg = NPU3_NTL_MISC_CFG2(dev->index);
 	val = npu3_read(npu, reg);
 	val |= NPU3_NTL_MISC_CFG2_BRICK_ENABLE |
-	       NPU3_NTL_MISC_CFG2_NDL_TX_PARITY_ENA |
-	       NPU3_NTL_MISC_CFG2_NDL_PRI_PARITY_ENA |
 	       NPU3_NTL_MISC_CFG2_RCV_CREDIT_OVERFLOW_ENA;
 	npu3_write(npu, reg, val);
 }