From patchwork Wed Jun 12 21:08:54 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Reza Arbab X-Patchwork-Id: 1114842 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [203.11.71.2]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 45PKKR55F2z9sBb for ; Thu, 13 Jun 2019 07:10:51 +1000 (AEST) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=linux.ibm.com Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 45PKKR37XVzDrBf for ; Thu, 13 Jun 2019 07:10:51 +1000 (AEST) X-Original-To: skiboot@lists.ozlabs.org Delivered-To: skiboot@lists.ozlabs.org Authentication-Results: lists.ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=linux.ibm.com (client-ip=148.163.156.1; helo=mx0a-001b2d01.pphosted.com; envelope-from=arbab@linux.ibm.com; receiver=) Authentication-Results: lists.ozlabs.org; dmarc=none (p=none dis=none) header.from=linux.ibm.com Received: from mx0a-001b2d01.pphosted.com (mx0a-001b2d01.pphosted.com [148.163.156.1]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 45PKHh4M76zDqtZ for ; Thu, 13 Jun 2019 07:09:20 +1000 (AEST) Received: from pps.filterd (m0098394.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.16.0.27/8.16.0.27) with SMTP id x5CL5bep104355 for ; Wed, 12 Jun 2019 17:09:18 -0400 Received: from e32.co.us.ibm.com (e32.co.us.ibm.com [32.97.110.150]) by mx0a-001b2d01.pphosted.com with ESMTP id 2t365u6mpc-1 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=NOT) for ; Wed, 12 Jun 2019 17:09:13 -0400 Received: from localhost by e32.co.us.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! 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Violators will be prosecuted; (version=TLSv1/SSLv3 cipher=AES256-GCM-SHA384 bits=256/256) Wed, 12 Jun 2019 22:09:00 +0100 Received: from b03ledav005.gho.boulder.ibm.com (b03ledav005.gho.boulder.ibm.com [9.17.130.236]) by b03cxnp08028.gho.boulder.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id x5CL8xr836503848 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Wed, 12 Jun 2019 21:08:59 GMT Received: from b03ledav005.gho.boulder.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 6D2BBBE054; Wed, 12 Jun 2019 21:08:59 +0000 (GMT) Received: from b03ledav005.gho.boulder.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 39774BE04F; Wed, 12 Jun 2019 21:08:59 +0000 (GMT) Received: from arbab-laptop.localdomain (unknown [9.53.179.210]) by b03ledav005.gho.boulder.ibm.com (Postfix) with ESMTP; Wed, 12 Jun 2019 21:08:59 +0000 (GMT) Received: by arbab-laptop.localdomain (Postfix, from userid 152845) id 23A0F465235; Wed, 12 Jun 2019 16:08:58 -0500 (CDT) From: Reza Arbab To: skiboot@lists.ozlabs.org Date: Wed, 12 Jun 2019 16:08:54 -0500 X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1560373737-21649-1-git-send-email-arbab@linux.ibm.com> References: <1560373737-21649-1-git-send-email-arbab@linux.ibm.com> X-TM-AS-GCONF: 00 x-cbid: 19061221-0004-0000-0000-0000151B93A7 X-IBM-SpamModules-Scores: X-IBM-SpamModules-Versions: BY=3.00011251; HX=3.00000242; KW=3.00000007; PH=3.00000004; SC=3.00000286; SDB=6.01217067; UDB=6.00639972; IPR=6.00998175; MB=3.00027285; MTD=3.00000008; XFM=3.00000015; UTC=2019-06-12 21:09:02 X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 19061221-0005-0000-0000-00008C10D226 Message-Id: <1560373737-21649-5-git-send-email-arbab@linux.ibm.com> X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:, , definitions=2019-06-12_13:, , signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 malwarescore=0 suspectscore=1 phishscore=0 bulkscore=0 spamscore=0 clxscore=1015 lowpriorityscore=0 mlxscore=0 impostorscore=0 mlxlogscore=999 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1810050000 definitions=main-1906120145 Subject: [Skiboot] [PATCH 4/7] npu2: Refactor NPU OPAL calls X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Michael Neuling , Andrew Donnellan , Alistair Popple , Christophe Lombard MIME-Version: 1.0 Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" Abstract the OPAL entry points for npu2, moving them to a new file. This prepares us to add parallel npu3 versions of the same APIs. No functional change. Signed-off-by: Reza Arbab Reviewed-by: Andrew Donnellan --- hw/Makefile.inc | 2 +- hw/npu-opal.c | 165 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++ hw/npu2.c | 149 ++++++-------------------------------------------- include/npu2.h | 8 +++ 4 files changed, 191 insertions(+), 133 deletions(-) create mode 100644 hw/npu-opal.c diff --git a/hw/Makefile.inc b/hw/Makefile.inc index 43e8b23c1b40..2f4f4dabef59 100644 --- a/hw/Makefile.inc +++ b/hw/Makefile.inc @@ -8,7 +8,7 @@ HW_OBJS += dts.o lpc-rtc.o npu.o npu-hw-procedures.o xive.o phb4.o HW_OBJS += fake-nvram.o lpc-mbox.o npu2.o npu2-hw-procedures.o HW_OBJS += npu2-common.o phys-map.o sbe-p9.o capp.o occ-sensor.o vas.o HW_OBJS += npu2-opencapi.o phys-map.o sbe-p9.o capp.o occ-sensor.o -HW_OBJS += vas.o sbe-p8.o dio-p9.o cache-p9.o +HW_OBJS += vas.o sbe-p8.o dio-p9.o cache-p9.o npu-opal.o HW_OBJS += lpc-port80h.o HW=hw/built-in.a diff --git a/hw/npu-opal.c b/hw/npu-opal.c new file mode 100644 index 000000000000..4195ffa2fc60 --- /dev/null +++ b/hw/npu-opal.c @@ -0,0 +1,165 @@ +/* Copyright 2019 IBM Corp. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + * implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include +#include +#include +#include + +static int64_t opal_npu_init_context(uint64_t phb_id, int pid __unused, + uint64_t msr, uint64_t bdf) +{ + struct phb *phb = pci_get_phb(phb_id); + + if (!phb || phb->phb_type != phb_type_npu_v2) + return OPAL_PARAMETER; + + return npu2_init_context(phb, msr, bdf); +} +opal_call(OPAL_NPU_INIT_CONTEXT, opal_npu_init_context, 4); + +static int64_t opal_npu_destroy_context(uint64_t phb_id, uint64_t pid __unused, + uint64_t bdf) +{ + struct phb *phb = pci_get_phb(phb_id); + + if (!phb || phb->phb_type != phb_type_npu_v2) + return OPAL_PARAMETER; + + return npu2_destroy_context(phb, bdf); +} +opal_call(OPAL_NPU_DESTROY_CONTEXT, opal_npu_destroy_context, 3); + +static int64_t opal_npu_map_lpar(uint64_t phb_id, uint64_t bdf, uint64_t lparid, + uint64_t lpcr) +{ + struct phb *phb = pci_get_phb(phb_id); + + if (!phb || phb->phb_type != phb_type_npu_v2) + return OPAL_PARAMETER; + + return npu2_map_lpar(phb, bdf, lparid, lpcr); +} +opal_call(OPAL_NPU_MAP_LPAR, opal_npu_map_lpar, 4); + +static int npu_check_relaxed_ordering(struct phb *phb, struct pci_device *pd, + void *enable) +{ + /* + * IBM PCIe bridge devices (ie. the root ports) can always allow relaxed + * ordering + */ + if (pd->vdid == 0x04c11014) + pd->allow_relaxed_ordering = true; + + PCIDBG(phb, pd->bdfn, "Checking relaxed ordering config\n"); + if (pd->allow_relaxed_ordering) + return 0; + + PCIDBG(phb, pd->bdfn, "Relaxed ordering not allowed\n"); + *(bool *)enable = false; + + return 1; +} + +static int64_t npu_set_relaxed_order(uint32_t gcid, int pec, bool enable) +{ + struct phb *phb; + uint64_t rc; + + for_each_phb(phb) { + if (phb->phb_type != phb_type_npu_v2) + continue; + + rc = npu2_set_relaxed_order(phb, gcid, pec, enable); + if (rc) + return rc; + } + + return OPAL_SUCCESS; +} + +static int64_t opal_npu_set_relaxed_order(uint64_t phb_id, uint16_t bdfn, + bool request_enabled) +{ + struct phb *phb = pci_get_phb(phb_id); + struct phb4 *phb4; + uint32_t chip_id, pec; + struct pci_device *pd; + bool enable = true; + + if (!phb || phb->phb_type != phb_type_pcie_v4) + return OPAL_PARAMETER; + + phb4 = phb_to_phb4(phb); + pec = phb4->pec; + chip_id = phb4->chip_id; + + if (chip_id & ~0x1b) + return OPAL_PARAMETER; + + pd = pci_find_dev(phb, bdfn); + if (!pd) + return OPAL_PARAMETER; + + /* + * Not changing state, so no need to rescan PHB devices to determine if + * we need to enable/disable it + */ + if (pd->allow_relaxed_ordering == request_enabled) + return OPAL_SUCCESS; + + pd->allow_relaxed_ordering = request_enabled; + + /* + * Walk all devices on this PHB to ensure they all support relaxed + * ordering + */ + pci_walk_dev(phb, NULL, npu_check_relaxed_ordering, &enable); + + if (request_enabled && !enable) { + /* + * Not all devices on this PHB support relaxed-ordering + * mode so we can't enable it as requested + */ + prlog(PR_INFO, "Cannot set relaxed ordering for PEC %d on chip %d\n", + pec, chip_id); + return OPAL_CONSTRAINED; + } + + if (npu_set_relaxed_order(chip_id, pec, request_enabled)) { + npu_set_relaxed_order(chip_id, pec, false); + return OPAL_RESOURCE; + } + + phb4->ro_state = request_enabled; + return OPAL_SUCCESS; +} +opal_call(OPAL_NPU_SET_RELAXED_ORDER, opal_npu_set_relaxed_order, 3); + +static int64_t opal_npu_get_relaxed_order(uint64_t phb_id, + uint16_t bdfn __unused) +{ + struct phb *phb = pci_get_phb(phb_id); + struct phb4 *phb4; + + if (!phb || phb->phb_type != phb_type_pcie_v4) + return OPAL_PARAMETER; + + phb4 = phb_to_phb4(phb); + return phb4->ro_state; +} +opal_call(OPAL_NPU_GET_RELAXED_ORDER, opal_npu_get_relaxed_order, 2); diff --git a/hw/npu2.c b/hw/npu2.c index 8edc29bfd99f..448561fdb030 100644 --- a/hw/npu2.c +++ b/hw/npu2.c @@ -1932,17 +1932,12 @@ static int npu_table_search(struct npu2 *p, uint64_t table_addr, int stride, * allocated. */ #define NPU2_VALID_ATS_MSR_BITS (MSR_DR | MSR_HV | MSR_PR | MSR_SF) -static int64_t opal_npu_init_context(uint64_t phb_id, int pasid __unused, - uint64_t msr, uint64_t bdf) +int64_t npu2_init_context(struct phb *phb, uint64_t msr, uint64_t bdf) { - struct phb *phb = pci_get_phb(phb_id); struct npu2 *p; uint64_t xts_bdf, old_xts_bdf_pid, xts_bdf_pid; int id; - if (!phb || phb->phb_type != phb_type_npu_v2) - return OPAL_PARAMETER; - /* * MSR bits should be masked by the caller to allow for future * expansion if required. @@ -2020,19 +2015,13 @@ out: unlock(&p->lock); return id; } -opal_call(OPAL_NPU_INIT_CONTEXT, opal_npu_init_context, 4); -static int opal_npu_destroy_context(uint64_t phb_id, uint64_t pid __unused, - uint64_t bdf) +int64_t npu2_destroy_context(struct phb *phb, uint64_t bdf) { - struct phb *phb = pci_get_phb(phb_id); struct npu2 *p; uint64_t xts_bdf; int rc = OPAL_PARAMETER, id; - if (!phb || phb->phb_type != phb_type_npu_v2) - return OPAL_PARAMETER; - p = phb_to_npu2_nvlink(phb); lock(&p->lock); @@ -2061,15 +2050,13 @@ static int opal_npu_destroy_context(uint64_t phb_id, uint64_t pid __unused, unlock(&p->lock); return rc; } -opal_call(OPAL_NPU_DESTROY_CONTEXT, opal_npu_destroy_context, 3); /* * Map the given virtual bdf to lparid with given lpcr. */ -static int opal_npu_map_lpar(uint64_t phb_id, uint64_t bdf, uint64_t lparid, - uint64_t lpcr) +int64_t npu2_map_lpar(struct phb *phb, uint64_t bdf, uint64_t lparid, + uint64_t lpcr) { - struct phb *phb = pci_get_phb(phb_id); struct npu2 *p; struct npu2_dev *ndev = NULL; uint64_t xts_bdf_lpar, atsd_lpar, rc = OPAL_SUCCESS; @@ -2082,9 +2069,6 @@ static int opal_npu_map_lpar(uint64_t phb_id, uint64_t bdf, uint64_t lparid, NPU2_XTS_MMIO_ATSD6_LPARID, NPU2_XTS_MMIO_ATSD7_LPARID }; - if (!phb || phb->phb_type != phb_type_npu_v2) - return OPAL_PARAMETER; - if (lpcr) /* The LPCR bits are only required for hash based ATS, * which we don't currently support but may need to in @@ -2167,7 +2151,6 @@ out: unlock(&p->lock); return rc; } -opal_call(OPAL_NPU_MAP_LPAR, opal_npu_map_lpar, 4); static inline uint32_t npu2_relaxed_ordering_source_grpchp(uint32_t gcid) { @@ -2313,123 +2296,25 @@ static void npu2_disable_relaxed_ordering(struct npu2_dev *ndev, uint32_t gcid, * relaxed ordering partially enabled if there are insufficient HW resources to * enable it on all links. */ -static int npu2_set_relaxed_ordering(uint32_t gcid, int pec, bool enable) +int64_t npu2_set_relaxed_order(struct phb *phb, uint32_t gcid, int pec, + bool enable) { - int rc = OPAL_SUCCESS; - struct phb *phb; - struct npu2 *npu; + struct npu2 *npu = phb_to_npu2_nvlink(phb); struct npu2_dev *ndev; + int64_t rc = OPAL_SUCCESS; - for_each_phb(phb) { - if (phb->phb_type != phb_type_npu_v2) - continue; + for (int i = 0; i < npu->total_devices; i++) { + ndev = &npu->devices[i]; + if (enable) + rc = npu2_enable_relaxed_ordering(ndev, gcid, pec); + else + npu2_disable_relaxed_ordering(ndev, gcid, pec); - npu = phb_to_npu2_nvlink(phb); - for (int i = 0; i < npu->total_devices; i++) { - ndev = &npu->devices[i]; - if (enable) - rc = npu2_enable_relaxed_ordering(ndev, gcid, pec); - else - npu2_disable_relaxed_ordering(ndev, gcid, pec); - - if (rc != OPAL_SUCCESS) { - NPU2DEVINF(ndev, "Insufficient resources to activate relaxed ordering mode\n"); - return OPAL_RESOURCE; - } + if (rc != OPAL_SUCCESS) { + NPU2DEVINF(ndev, "Insufficient resources to activate relaxed ordering mode\n"); + return OPAL_RESOURCE; } } return OPAL_SUCCESS; } - -static int npu2_check_relaxed_ordering(struct phb *phb __unused, - struct pci_device *pd, void *enable) -{ - /* - * IBM PCIe bridge devices (ie. the root ports) can always allow relaxed - * ordering - */ - if (pd->vdid == 0x04c11014) - pd->allow_relaxed_ordering = true; - - PCIDBG(phb, pd->bdfn, "Checking relaxed ordering config\n"); - if (pd->allow_relaxed_ordering) - return 0; - - PCIDBG(phb, pd->bdfn, "Relaxed ordering not allowed\n"); - *(bool *) enable = false; - - return 1; -} - -static int64_t opal_npu_set_relaxed_order(uint64_t phb_id, uint16_t bdfn, - bool request_enabled) -{ - struct phb *phb = pci_get_phb(phb_id); - struct phb4 *phb4; - uint32_t chip_id, pec; - struct pci_device *pd; - bool enable = true; - - if (!phb || phb->phb_type != phb_type_pcie_v4) - return OPAL_PARAMETER; - - phb4 = phb_to_phb4(phb); - pec = phb4->pec; - chip_id = phb4->chip_id; - - if (npu2_relaxed_ordering_source_grpchp(chip_id) == OPAL_PARAMETER) - return OPAL_PARAMETER; - - pd = pci_find_dev(phb, bdfn); - if (!pd) - return OPAL_PARAMETER; - - /* - * Not changing state, so no need to rescan PHB devices to determine if - * we need to enable/disable it - */ - if (pd->allow_relaxed_ordering == request_enabled) - return OPAL_SUCCESS; - - pd->allow_relaxed_ordering = request_enabled; - - /* - * Walk all devices on this PHB to ensure they all support relaxed - * ordering - */ - pci_walk_dev(phb, NULL, npu2_check_relaxed_ordering, &enable); - - if (request_enabled && !enable) { - /* - * Not all devices on this PHB support relaxed-ordering - * mode so we can't enable it as requested - */ - prlog(PR_INFO, "Cannot set relaxed ordering for PEC %d on chip %d\n", - pec, chip_id); - return OPAL_CONSTRAINED; - } - - if (npu2_set_relaxed_ordering(chip_id, pec, request_enabled) != OPAL_SUCCESS) { - npu2_set_relaxed_ordering(chip_id, pec, false); - return OPAL_RESOURCE; - } - - phb4->ro_state = request_enabled; - return OPAL_SUCCESS; -} -opal_call(OPAL_NPU_SET_RELAXED_ORDER, opal_npu_set_relaxed_order, 3); - -static int64_t opal_npu_get_relaxed_order(uint64_t phb_id, - uint16_t bdfn __unused) -{ - struct phb *phb = pci_get_phb(phb_id); - struct phb4 *phb4; - - if (!phb || phb->phb_type != phb_type_pcie_v4) - return OPAL_PARAMETER; - - phb4 = phb_to_phb4(phb); - return phb4->ro_state; -} -opal_call(OPAL_NPU_GET_RELAXED_ORDER, opal_npu_get_relaxed_order, 2); diff --git a/include/npu2.h b/include/npu2.h index 5b2a436bda06..21a61712b5b9 100644 --- a/include/npu2.h +++ b/include/npu2.h @@ -256,4 +256,12 @@ int64_t npu2_freeze_status(struct phb *phb __unused, uint16_t *pci_error_type __unused, uint16_t *severity __unused); void npu2_dump_scoms(int chip_id); + +int64_t npu2_init_context(struct phb *phb, uint64_t msr, uint64_t bdf); +int64_t npu2_destroy_context(struct phb *phb, uint64_t bdf); +int64_t npu2_map_lpar(struct phb *phb, uint64_t bdf, uint64_t lparid, + uint64_t lpcr); +int64_t npu2_set_relaxed_order(struct phb *phb, uint32_t gcid, int pec, + bool enable); + #endif /* __NPU2_H */