From patchwork Wed Jun 12 21:08:53 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Reza Arbab X-Patchwork-Id: 1114839 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 45PKJd5Ph6z9s4Y for ; Thu, 13 Jun 2019 07:10:09 +1000 (AEST) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=linux.ibm.com Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 45PKJd4ZCCzDr75 for ; Thu, 13 Jun 2019 07:10:09 +1000 (AEST) X-Original-To: skiboot@lists.ozlabs.org Delivered-To: skiboot@lists.ozlabs.org Authentication-Results: lists.ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=linux.ibm.com (client-ip=148.163.158.5; helo=mx0a-001b2d01.pphosted.com; envelope-from=arbab@linux.ibm.com; receiver=) Authentication-Results: lists.ozlabs.org; dmarc=none (p=none dis=none) header.from=linux.ibm.com Received: from mx0a-001b2d01.pphosted.com (mx0b-001b2d01.pphosted.com [148.163.158.5]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 45PKHR3nrQzDqsb for ; Thu, 13 Jun 2019 07:09:07 +1000 (AEST) Received: from pps.filterd (m0098419.ppops.net [127.0.0.1]) by mx0b-001b2d01.pphosted.com (8.16.0.27/8.16.0.27) with SMTP id x5CL7hbL089121 for ; Wed, 12 Jun 2019 17:09:04 -0400 Received: from e17.ny.us.ibm.com (e17.ny.us.ibm.com [129.33.205.207]) by mx0b-001b2d01.pphosted.com with ESMTP id 2t35nefrr3-1 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=NOT) for ; Wed, 12 Jun 2019 17:09:04 -0400 Received: from localhost by e17.ny.us.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! 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Violators will be prosecuted; (version=TLSv1/SSLv3 cipher=AES256-GCM-SHA384 bits=256/256) Wed, 12 Jun 2019 22:09:00 +0100 Received: from b01ledav006.gho.pok.ibm.com (b01ledav006.gho.pok.ibm.com [9.57.199.111]) by b01cxnp23032.gho.pok.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id x5CL8x7o11534776 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Wed, 12 Jun 2019 21:08:59 GMT Received: from b01ledav006.gho.pok.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 55FF3AC062; Wed, 12 Jun 2019 21:08:59 +0000 (GMT) Received: from b01ledav006.gho.pok.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 30086AC05E; Wed, 12 Jun 2019 21:08:59 +0000 (GMT) Received: from arbab-laptop.localdomain (unknown [9.53.179.210]) by b01ledav006.gho.pok.ibm.com (Postfix) with ESMTP; Wed, 12 Jun 2019 21:08:59 +0000 (GMT) Received: by arbab-laptop.localdomain (Postfix, from userid 152845) id 18BF6465234; Wed, 12 Jun 2019 16:08:58 -0500 (CDT) From: Reza Arbab To: skiboot@lists.ozlabs.org Date: Wed, 12 Jun 2019 16:08:53 -0500 X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1560373737-21649-1-git-send-email-arbab@linux.ibm.com> References: <1560373737-21649-1-git-send-email-arbab@linux.ibm.com> X-TM-AS-GCONF: 00 x-cbid: 19061221-0040-0000-0000-000004FC521D X-IBM-SpamModules-Scores: X-IBM-SpamModules-Versions: BY=3.00011251; HX=3.00000242; KW=3.00000007; PH=3.00000004; SC=3.00000286; SDB=6.01217067; UDB=6.00639972; IPR=6.00998175; MB=3.00027285; MTD=3.00000008; XFM=3.00000015; UTC=2019-06-12 21:09:02 X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 19061221-0041-0000-0000-000009087875 Message-Id: <1560373737-21649-4-git-send-email-arbab@linux.ibm.com> X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:, , definitions=2019-06-12_13:, , signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 malwarescore=0 suspectscore=1 phishscore=0 bulkscore=0 spamscore=0 clxscore=1015 lowpriorityscore=0 mlxscore=0 impostorscore=0 mlxlogscore=999 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1810050000 definitions=main-1906120145 Subject: [Skiboot] [PATCH 3/7] npu2: Prepare purge_l2_l3_caches() for reuse X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Michael Neuling , Andrew Donnellan , Alistair Popple , Christophe Lombard MIME-Version: 1.0 Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" Move this to a separate compilation unit with its own header, for reuse. Signed-off-by: Reza Arbab Reviewed-by: Andrew Donnellan --- hw/Makefile.inc | 2 +- hw/cache-p9.c | 165 ++++++++++++++++++++++++++++++++++++++++++++++++++++ hw/npu2.c | 133 +----------------------------------------- include/cache-p9.h | 22 +++++++ include/npu2-regs.h | 11 ---- 5 files changed, 189 insertions(+), 144 deletions(-) create mode 100644 hw/cache-p9.c create mode 100644 include/cache-p9.h diff --git a/hw/Makefile.inc b/hw/Makefile.inc index 0e8c257fb80a..43e8b23c1b40 100644 --- a/hw/Makefile.inc +++ b/hw/Makefile.inc @@ -8,7 +8,7 @@ HW_OBJS += dts.o lpc-rtc.o npu.o npu-hw-procedures.o xive.o phb4.o HW_OBJS += fake-nvram.o lpc-mbox.o npu2.o npu2-hw-procedures.o HW_OBJS += npu2-common.o phys-map.o sbe-p9.o capp.o occ-sensor.o vas.o HW_OBJS += npu2-opencapi.o phys-map.o sbe-p9.o capp.o occ-sensor.o -HW_OBJS += vas.o sbe-p8.o dio-p9.o +HW_OBJS += vas.o sbe-p8.o dio-p9.o cache-p9.o HW_OBJS += lpc-port80h.o HW=hw/built-in.a diff --git a/hw/cache-p9.c b/hw/cache-p9.c new file mode 100644 index 000000000000..4631c11ab39e --- /dev/null +++ b/hw/cache-p9.c @@ -0,0 +1,165 @@ +/* Copyright 2019 IBM Corp. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + * implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include +#include +#include +#include +#include +#include + +/* Registers and bits used to clear the L2 and L3 cache */ +#define L2_PRD_PURGE_CMD_REG 0x1080e +#define L2_PRD_PURGE_CMD_TRIGGER PPC_BIT(0) +#define L2_PRD_PURGE_CMD_TYPE_MASK PPC_BITMASK(1, 4) +#define L2CAC_FLUSH 0x0 +#define L2_PRD_PURGE_CMD_REG_BUSY PPC_BIT(9) +#define L3_PRD_PURGE_REG 0x1180e +#define L3_PRD_PURGE_REQ PPC_BIT(0) +#define L3_PRD_PURGE_TTYPE_MASK PPC_BITMASK(1, 4) +#define L3_FULL_PURGE 0x0 + +static int start_l2_purge(uint32_t chip_id, uint32_t core_id) +{ + uint64_t addr = XSCOM_ADDR_P9_EX(core_id, L2_PRD_PURGE_CMD_REG); + int rc; + + rc = xscom_write_mask(chip_id, addr, L2CAC_FLUSH, + L2_PRD_PURGE_CMD_TYPE_MASK); + if (!rc) + rc = xscom_write_mask(chip_id, addr, L2_PRD_PURGE_CMD_TRIGGER, + L2_PRD_PURGE_CMD_TRIGGER); + if (rc) + prlog(PR_ERR, "PURGE L2 on core 0x%x: XSCOM write_mask " + "failed %i\n", core_id, rc); + return rc; +} + +static int wait_l2_purge(uint32_t chip_id, uint32_t core_id) +{ + uint64_t val; + uint64_t addr = XSCOM_ADDR_P9_EX(core_id, L2_PRD_PURGE_CMD_REG); + unsigned long now = mftb(); + unsigned long end = now + msecs_to_tb(2); + int rc; + + while (1) { + rc = xscom_read(chip_id, addr, &val); + if (rc) { + prlog(PR_ERR, "PURGE L2 on core 0x%x: XSCOM read " + "failed %i\n", core_id, rc); + break; + } + if (!(val & L2_PRD_PURGE_CMD_REG_BUSY)) + break; + now = mftb(); + if (tb_compare(now, end) == TB_AAFTERB) { + prlog(PR_ERR, "PURGE L2 on core 0x%x timed out %i\n", + core_id, rc); + return OPAL_BUSY; + } + } + + /* We have to clear the trigger bit ourselves */ + val &= ~L2_PRD_PURGE_CMD_TRIGGER; + rc = xscom_write(chip_id, addr, val); + if (rc) + prlog(PR_ERR, "PURGE L2 on core 0x%x: XSCOM write failed %i\n", + core_id, rc); + return rc; +} + +static int start_l3_purge(uint32_t chip_id, uint32_t core_id) +{ + uint64_t addr = XSCOM_ADDR_P9_EX(core_id, L3_PRD_PURGE_REG); + int rc; + + rc = xscom_write_mask(chip_id, addr, L3_FULL_PURGE, + L3_PRD_PURGE_TTYPE_MASK); + if (!rc) + rc = xscom_write_mask(chip_id, addr, L3_PRD_PURGE_REQ, + L3_PRD_PURGE_REQ); + if (rc) + prlog(PR_ERR, "PURGE L3 on core 0x%x: XSCOM write_mask " + "failed %i\n", core_id, rc); + return rc; +} + +static int wait_l3_purge(uint32_t chip_id, uint32_t core_id) +{ + uint64_t val; + uint64_t addr = XSCOM_ADDR_P9_EX(core_id, L3_PRD_PURGE_REG); + unsigned long now = mftb(); + unsigned long end = now + msecs_to_tb(2); + int rc; + + /* Trigger bit is automatically set to zero when flushing is done */ + while (1) { + rc = xscom_read(chip_id, addr, &val); + if (rc) { + prlog(PR_ERR, "PURGE L3 on core 0x%x: XSCOM read " + "failed %i\n", core_id, rc); + break; + } + if (!(val & L3_PRD_PURGE_REQ)) + break; + now = mftb(); + if (tb_compare(now, end) == TB_AAFTERB) { + prlog(PR_ERR, "PURGE L3 on core 0x%x timed out %i\n", + core_id, rc); + return OPAL_BUSY; + } + } + return rc; +} + +int64_t purge_l2_l3_caches(void) +{ + struct cpu_thread *t; + uint64_t core_id, prev_core_id = (uint64_t)-1; + int rc; + + for_each_ungarded_cpu(t) { + /* Only need to do it once per core chiplet */ + core_id = pir_to_core_id(t->pir); + if (prev_core_id == core_id) + continue; + prev_core_id = core_id; + rc = start_l2_purge(t->chip_id, core_id); + if (rc) + return rc; + rc = start_l3_purge(t->chip_id, core_id); + if (rc) + return rc; + } + + prev_core_id = (uint64_t)-1; + for_each_ungarded_cpu(t) { + /* Only need to do it once per core chiplet */ + core_id = pir_to_core_id(t->pir); + if (prev_core_id == core_id) + continue; + prev_core_id = core_id; + + rc = wait_l2_purge(t->chip_id, core_id); + if (rc) + return rc; + rc = wait_l3_purge(t->chip_id, core_id); + if (rc) + return rc; + } + return OPAL_SUCCESS; +} diff --git a/hw/npu2.c b/hw/npu2.c index ee2b4b21ef40..8edc29bfd99f 100644 --- a/hw/npu2.c +++ b/hw/npu2.c @@ -36,6 +36,7 @@ #include #include #include +#include #define VENDOR_CAP_START 0x80 #define VENDOR_CAP_END 0x90 @@ -315,138 +316,6 @@ static int64_t npu2_dev_cfg_bar(void *dev, struct pci_cfg_reg_filter *pcrf, return npu2_cfg_read_bar(ndev, pcrf, offset, len, data); } -static int start_l2_purge(uint32_t chip_id, uint32_t core_id) -{ - uint64_t addr = XSCOM_ADDR_P9_EX(core_id, L2_PRD_PURGE_CMD_REG); - int rc; - - rc = xscom_write_mask(chip_id, addr, L2CAC_FLUSH, - L2_PRD_PURGE_CMD_TYPE_MASK); - if (!rc) - rc = xscom_write_mask(chip_id, addr, L2_PRD_PURGE_CMD_TRIGGER, - L2_PRD_PURGE_CMD_TRIGGER); - if (rc) - prlog(PR_ERR, "PURGE L2 on core 0x%x: XSCOM write_mask " - "failed %i\n", core_id, rc); - return rc; -} - -static int wait_l2_purge(uint32_t chip_id, uint32_t core_id) -{ - uint64_t val; - uint64_t addr = XSCOM_ADDR_P9_EX(core_id, L2_PRD_PURGE_CMD_REG); - unsigned long now = mftb(); - unsigned long end = now + msecs_to_tb(2); - int rc; - - while (1) { - rc = xscom_read(chip_id, addr, &val); - if (rc) { - prlog(PR_ERR, "PURGE L2 on core 0x%x: XSCOM read " - "failed %i\n", core_id, rc); - break; - } - if (!(val & L2_PRD_PURGE_CMD_REG_BUSY)) - break; - now = mftb(); - if (tb_compare(now, end) == TB_AAFTERB) { - prlog(PR_ERR, "PURGE L2 on core 0x%x timed out %i\n", - core_id, rc); - return OPAL_BUSY; - } - } - - /* We have to clear the trigger bit ourselves */ - val &= ~L2_PRD_PURGE_CMD_TRIGGER; - rc = xscom_write(chip_id, addr, val); - if (rc) - prlog(PR_ERR, "PURGE L2 on core 0x%x: XSCOM write failed %i\n", - core_id, rc); - return rc; -} - -static int start_l3_purge(uint32_t chip_id, uint32_t core_id) -{ - uint64_t addr = XSCOM_ADDR_P9_EX(core_id, L3_PRD_PURGE_REG); - int rc; - - rc = xscom_write_mask(chip_id, addr, L3_FULL_PURGE, - L3_PRD_PURGE_TTYPE_MASK); - if (!rc) - rc = xscom_write_mask(chip_id, addr, L3_PRD_PURGE_REQ, - L3_PRD_PURGE_REQ); - if (rc) - prlog(PR_ERR, "PURGE L3 on core 0x%x: XSCOM write_mask " - "failed %i\n", core_id, rc); - return rc; -} - -static int wait_l3_purge(uint32_t chip_id, uint32_t core_id) -{ - uint64_t val; - uint64_t addr = XSCOM_ADDR_P9_EX(core_id, L3_PRD_PURGE_REG); - unsigned long now = mftb(); - unsigned long end = now + msecs_to_tb(2); - int rc; - - /* Trigger bit is automatically set to zero when flushing is done */ - while (1) { - rc = xscom_read(chip_id, addr, &val); - if (rc) { - prlog(PR_ERR, "PURGE L3 on core 0x%x: XSCOM read " - "failed %i\n", core_id, rc); - break; - } - if (!(val & L3_PRD_PURGE_REQ)) - break; - now = mftb(); - if (tb_compare(now, end) == TB_AAFTERB) { - prlog(PR_ERR, "PURGE L3 on core 0x%x timed out %i\n", - core_id, rc); - return OPAL_BUSY; - } - } - return rc; -} - -static int64_t purge_l2_l3_caches(void) -{ - struct cpu_thread *t; - uint64_t core_id, prev_core_id = (uint64_t)-1; - int rc; - - for_each_ungarded_cpu(t) { - /* Only need to do it once per core chiplet */ - core_id = pir_to_core_id(t->pir); - if (prev_core_id == core_id) - continue; - prev_core_id = core_id; - rc = start_l2_purge(t->chip_id, core_id); - if (rc) - return rc; - rc = start_l3_purge(t->chip_id, core_id); - if (rc) - return rc; - } - - prev_core_id = (uint64_t)-1; - for_each_ungarded_cpu(t) { - /* Only need to do it once per core chiplet */ - core_id = pir_to_core_id(t->pir); - if (prev_core_id == core_id) - continue; - prev_core_id = core_id; - - rc = wait_l2_purge(t->chip_id, core_id); - if (rc) - return rc; - rc = wait_l3_purge(t->chip_id, core_id); - if (rc) - return rc; - } - return OPAL_SUCCESS; -} - static int64_t npu2_dev_cfg_exp_devcap(void *dev, struct pci_cfg_reg_filter *pcrf __unused, uint32_t offset, uint32_t size, diff --git a/include/cache-p9.h b/include/cache-p9.h new file mode 100644 index 000000000000..e763433b6b4e --- /dev/null +++ b/include/cache-p9.h @@ -0,0 +1,22 @@ +/* Copyright 2019 IBM Corp. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + * implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CACHE_P9_H +#define __CACHE_P9_H + +int64_t purge_l2_l3_caches(void); + +#endif diff --git a/include/npu2-regs.h b/include/npu2-regs.h index 3cb587adc354..ba2abe1e0cf2 100644 --- a/include/npu2-regs.h +++ b/include/npu2-regs.h @@ -787,17 +787,6 @@ void npu2_scom_write(uint64_t gcid, uint64_t scom_base, #define OB_ODL_ENDPOINT_INFO(brick_index) \ (0x9010832 + OB_ODL_OFFSET(brick_index)) -/* Registers and bits used to clear the L2 and L3 cache */ -#define L2_PRD_PURGE_CMD_REG 0x1080E -#define L2_PRD_PURGE_CMD_REG_BUSY 0x0040000000000000UL -#define L2_PRD_PURGE_CMD_TYPE_MASK PPC_BIT(1) | PPC_BIT(2) | PPC_BIT(3) | PPC_BIT(4) -#define L2_PRD_PURGE_CMD_TRIGGER PPC_BIT(0) -#define L2CAC_FLUSH 0x0 -#define L3_PRD_PURGE_REG 0x1180E -#define L3_PRD_PURGE_REQ PPC_BIT(0) -#define L3_PRD_PURGE_TTYPE_MASK PPC_BIT(1) | PPC_BIT(2) | PPC_BIT(3) | PPC_BIT(4) -#define L3_FULL_PURGE 0x0 - /* Config registers for NPU2 */ #define NPU_STCK0_CS_SM0_MISC_CONFIG0 0x5011000 #define NPU_STCK0_CS_SM1_MISC_CONFIG0 0x5011030