From patchwork Wed Feb 13 21:42:36 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Reza Arbab X-Patchwork-Id: 1041590 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 440ChZ5R7lz9rxp for ; Thu, 14 Feb 2019 08:43:58 +1100 (AEDT) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=linux.ibm.com Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 440ChZ45cZzDqTp for ; Thu, 14 Feb 2019 08:43:58 +1100 (AEDT) X-Original-To: skiboot@lists.ozlabs.org Delivered-To: skiboot@lists.ozlabs.org Authentication-Results: lists.ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=linux.ibm.com (client-ip=148.163.156.1; helo=mx0a-001b2d01.pphosted.com; envelope-from=arbab@linux.ibm.com; receiver=) Authentication-Results: lists.ozlabs.org; dmarc=none (p=none dis=none) header.from=linux.ibm.com Received: from mx0a-001b2d01.pphosted.com (mx0a-001b2d01.pphosted.com [148.163.156.1]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 440Cg95vS3zDqSV for ; Thu, 14 Feb 2019 08:42:45 +1100 (AEDT) Received: from pps.filterd (m0098404.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.16.0.27/8.16.0.27) with SMTP id x1DLcgrq090740 for ; Wed, 13 Feb 2019 16:42:43 -0500 Received: from e11.ny.us.ibm.com (e11.ny.us.ibm.com [129.33.205.201]) by mx0a-001b2d01.pphosted.com with ESMTP id 2qmu440map-1 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=NOT) for ; Wed, 13 Feb 2019 16:42:43 -0500 Received: from localhost by e11.ny.us.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! 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Violators will be prosecuted; (version=TLSv1/SSLv3 cipher=AES256-GCM-SHA384 bits=256/256) Wed, 13 Feb 2019 21:42:40 -0000 Received: from b01ledav004.gho.pok.ibm.com (b01ledav004.gho.pok.ibm.com [9.57.199.109]) by b01cxnp22034.gho.pok.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id x1DLgda421692626 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Wed, 13 Feb 2019 21:42:39 GMT Received: from b01ledav004.gho.pok.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 624AB112064; Wed, 13 Feb 2019 21:42:39 +0000 (GMT) Received: from b01ledav004.gho.pok.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 3A6B4112061; Wed, 13 Feb 2019 21:42:39 +0000 (GMT) Received: from arbab-laptop.localdomain (unknown [9.53.179.210]) by b01ledav004.gho.pok.ibm.com (Postfix) with ESMTP; Wed, 13 Feb 2019 21:42:39 +0000 (GMT) Received: by arbab-laptop.localdomain (Postfix, from userid 152845) id 328384608C6; Wed, 13 Feb 2019 15:42:38 -0600 (CST) From: Reza Arbab To: skiboot@lists.ozlabs.org Date: Wed, 13 Feb 2019 15:42:36 -0600 X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1550094158-29410-1-git-send-email-arbab@linux.ibm.com> References: <1550094158-29410-1-git-send-email-arbab@linux.ibm.com> X-TM-AS-GCONF: 00 x-cbid: 19021321-2213-0000-0000-00000350461B X-IBM-SpamModules-Scores: X-IBM-SpamModules-Versions: BY=3.00010590; HX=3.00000242; KW=3.00000007; PH=3.00000004; SC=3.00000279; SDB=6.01160630; UDB=6.00605774; IPR=6.00941184; MB=3.00025568; MTD=3.00000008; XFM=3.00000015; UTC=2019-02-13 21:42:41 X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 19021321-2214-0000-0000-00005D58C8C8 Message-Id: <1550094158-29410-5-git-send-email-arbab@linux.ibm.com> X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:, , definitions=2019-02-13_12:, , signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 malwarescore=0 suspectscore=1 phishscore=0 bulkscore=0 spamscore=0 clxscore=1015 lowpriorityscore=0 mlxscore=0 impostorscore=0 mlxlogscore=999 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1810050000 definitions=main-1902130142 Subject: [Skiboot] [PATCH 4/6] devicetree: Move power9-phb4.dts X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alistair Popple MIME-Version: 1.0 Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" Clean up the formatting of power9-phb4.dts and move it to external/devicetree/p9.dts. This sets us up to include it as the basis for other trees. Signed-off-by: Reza Arbab --- doc/device-tree/examples/power9-phb4.dts | 235 ------------------------------- external/devicetree/p9.dts | 221 +++++++++++++++++++++++++++++ 2 files changed, 221 insertions(+), 235 deletions(-) delete mode 100644 doc/device-tree/examples/power9-phb4.dts create mode 100644 external/devicetree/p9.dts diff --git a/doc/device-tree/examples/power9-phb4.dts b/doc/device-tree/examples/power9-phb4.dts deleted file mode 100644 index a6acd533970c..000000000000 --- a/doc/device-tree/examples/power9-phb4.dts +++ /dev/null @@ -1,235 +0,0 @@ -/dts-v1/; - -/ { - compatible = "ibm,powernv"; - model = "BML"; - #size-cells = <0x2>; - #address-cells = <0x2>; - - chosen { - linux,pci-assign-all-buses = <0x1>; - linux,pci-probe-only = <0x0>; - linux,platform = <0x100>; - ibm,architecture-vec-5 = <0x0 0x800000>; - linux,initrd-start = <0x0 0x28000000>; - linux,initrd-end = <0x0 0x30000000>; - }; - - memory@0 { - reg = <0x0 0x0 0x0 0x80000000>; - ibm,chip-id = <0x0>; - device_type = "memory"; - }; - - cpus { - #size-cells = <0x0>; - #address-cells = <0x1>; - - PowerPC,POWER9@0 { - device_type = "cpu"; - status = "okay"; - ibm,chip-id = <0x0>; - ibm,pir = <0x0>; - timebase-frequency = <0x1c4fecc0>; - clock-frequency = <0xe27f6600>; - ibm,segment-page-sizes = <0xc 0x0 0x1 0xc 0x0 0x10 0x110 0x1 0x10 0x1 0x14 0x111 0x1 0x14 0x2 0x18 0x100 0x1 0x18 0x0 0x22 0x120 0x1 0x22 0x3>; - ibm,processor-segment-sizes = <0x1c 0xffffffff 0xffffffff 0xffffffff>; - ibm,pa-features = <0x600f63f 0xc70080c0>; - i-cache-size = <0x8000>; - d-cache-size = <0x8000>; - i-cache-line-size = <0x80>; - d-cache-line-size = <0x80>; - ibm,slb-size = <0x20>; - ibm,vmx = <0x2>; - reg = <0x0>; -// ibm,ppc-interrupt-server#s = <0x0 0x01>; - ibm,ppc-interrupt-server#s = <0x0>; - }; - }; - - xscom@603fc00000000 { - compatible = "ibm,xscom", "ibm,power9-xscom"; - ibm,chip-id = <0x0>; - #size-cells = <0x1>; - #address-cells = <0x1>; - reg = <0x603fc 0x0 0x8 0x0>; - - - /* PE#0 supports only one stack */ - pbcq@4010c00 { - ibm,pec-index = <0x0>; - reg = <0x4010c00 0x100 0xd010800 0x200>; - compatible = "ibm,power9-pbcq"; - - /* child address is stack number */ - #address-cells = <1>; - #size-cells = <0>; - stack@0 { - /* Stack number */ - reg = <0>; - /* Chip-scope PHB index */ - ibm,phb-index = <0x0>; - compatible = "ibm,power9-phb-stack"; - /* ibm,lane-eq = < ????? >; */ - status = "okay"; - }; - }; - /* PE#1 supports two stacks */ - - pbcq@4011000 { - ibm,pec-index = <0x1>; - reg = <0x4011000 0x100 0xe010800 0x200>; - compatible = "ibm,power9-pbcq"; - - /* child address is stack number */ - #address-cells = <1>; - #size-cells = <0>; - stack@0 { - /* Stack number */ - reg = <0>; - /* Chip-scope PHB index */ - ibm,phb-index = <0x1>; - compatible = "ibm,power9-phb-stack"; - /* ibm,lane-eq = < ????? >; */ - status = "okay"; - }; - stack@1 { - /* Stack number */ - reg = <1>; - /* Chip-scope PHB index */ - ibm,phb-index = <0x2>; - compatible = "ibm,power9-phb-stack"; - /* ibm,lane-eq = < ????? >; */ - status = "okay"; - }; - }; - - /* PE#2 supports three stacks */ - pbcq@4011400 { - ibm,pec-index = <0x2>; - reg = <0x4011400 0x100 0xf010800 0x200>; - compatible = "ibm,power9-pbcq"; - - /* child address is stack number */ - #address-cells = <1>; - #size-cells = <0>; - stack@0 { - /* Stack number */ - reg = <0>; - /* Chip-scope PHB index */ - ibm,phb-index = <0x3>; - compatible = "ibm,power9-phb-stack"; - /* ibm,lane-eq = < ????? >; */ - status = "disabled"; - }; - stack@1 { - /* Stack number */ - reg = <1>; - /* Chip-scope PHB index */ - ibm,phb-index = <0x4>; - compatible = "ibm,power9-phb-stack"; - /* ibm,lane-eq = < ????? >; */ - status = "disabled"; - }; - stack@2 { - /* Stack number */ - reg = <2>; - /* Chip-scope PHB index */ - ibm,phb-index = <0x5>; - compatible = "ibm,power9-phb-stack"; - /* ibm,lane-eq = < ????? >; */ - status = "disabled"; - }; - }; - - chiptod@40000 { - primary; - reg = <0x40000 0x34>; - compatible = "ibm,power-chiptod", "ibm,power9-chiptod"; - }; - - xive@5013400 { - reg = <0x5013000 0x300>; - compatible = "ibm,power9-xive-x"; - }; - - PSI_X0: psihb@5012900 { - reg = <0x5012900 0x100>; - compatible = "ibm,power9-psihb-x", "ibm,psihb-x"; - - /* This acts as an interrupt remapper for the 16 - * interrupts coming into the PSI HB. - * OPAL will generate the corresponding interrupt-map - * property with the final XIVE numbers - */ - #interrupt-cells = <1>; - #address-cells = <0>; - #interrupt-map-mask = < 0xff >; - }; - - nx@2010000 { - reg = <0x2010000 0x4000>; - compatible = "ibm,power9-nx"; - }; - }; - - lpcm-opb@6030000000000 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "ibm,power9-lpcm-opb", "simple-bus"; - ibm,chip-id = <0x0>; - ranges = < 0x00000000 0x60300 0x00000000 0x80000000 - 0x80000000 0x60300 0x80000000 0x80000000 >; - opb-master@c0010000 { - compatible = "ibm,power9-lpcm-opb-master"; - reg = < 0xc0010000 0x60 >; - }; - opb-arbiter@c0011000 { - compatible = "ibm,power9-lpcm-opb-arbiter"; - reg = < 0xc0011000 0x8 >; - }; - lpc-controller@c0012000 { - compatible = "ibm,power9-lpc-controller"; - reg = < 0xc0012000 0x100 >; - }; - lpc@f0000000 { - compatible = "ibm,power9-lpc"; - #address-cells = <2>; - #size-cells = <1>; - ranges = < 3 0 0xf0000000 0x10000000 /* FW space */ - 0 0 0xe0000000 0x10000000 /* MEM space */ - 1 0 0xd0010000 0x00010000 /* IO space */ >; - - /* We currently only support level interrupts on the LPC, - * we use 1 cell. - */ - #interrupt-cells = <1>; - - /* Route the LPC interrupts to one of the 4 supported - * PSI interrupt inputs [7...10]. - */ - interrupt-map = < 0 0 4 &PSI_X0 8 - 0 0 10 &PSI_X0 9>; - interrupt-map-mask = < 0 0 0xff >; - - /* - * Devices on the LPC bus go here - */ - - serial@i3f8 { - compatible = "ns16550"; - reg = < 1 0x3f8 0x10 >; - current-speed = < 115200 >; - clock-frequency = < 1843200 >; - interrupts = <4>; - }; - - ipmi@ie4 { - compatible = "ipmi-bt"; - reg = < 1 0xe4 0x3 >; - interrupts = <10>; - }; - }; - }; - -}; diff --git a/external/devicetree/p9.dts b/external/devicetree/p9.dts new file mode 100644 index 000000000000..905e33d57aae --- /dev/null +++ b/external/devicetree/p9.dts @@ -0,0 +1,221 @@ +/dts-v1/; + +/ { + compatible = "ibm,powernv"; + model = "BML"; + #size-cells = <0x2>; + #address-cells = <0x2>; + + chosen { + linux,pci-assign-all-buses = <0x1>; + linux,pci-probe-only = <0x0>; + linux,platform = <0x100>; + ibm,architecture-vec-5 = <0x0 0x800000>; + linux,initrd-start = <0x0 0x28000000>; + linux,initrd-end = <0x0 0x30000000>; + }; + + memory@0 { + reg = <0x0 0x0 0x0 0x80000000>; + ibm,chip-id = <0x0>; + device_type = "memory"; + }; + + cpus { + #size-cells = <0x0>; + #address-cells = <0x1>; + + PowerPC,POWER9@0 { + device_type = "cpu"; + status = "okay"; + ibm,chip-id = <0x0>; + ibm,pir = <0x0>; + timebase-frequency = <0x1c4fecc0>; + clock-frequency = <0xe27f6600>; + ibm,segment-page-sizes = <0xc 0x0 0x1 0xc 0x0 0x10 0x110 0x1 0x10 0x1 0x14 0x111 0x1 0x14 0x2 0x18 0x100 0x1 0x18 0x0 0x22 0x120 0x1 0x22 0x3>; + ibm,processor-segment-sizes = <0x1c 0xffffffff 0xffffffff 0xffffffff>; + ibm,pa-features = <0x600f63f 0xc70080c0>; + i-cache-size = <0x8000>; + d-cache-size = <0x8000>; + i-cache-line-size = <0x80>; + d-cache-line-size = <0x80>; + ibm,slb-size = <0x20>; + ibm,vmx = <0x2>; + reg = <0x0>; + ibm,ppc-interrupt-server#s = <0x0>; + }; + }; + + xscom@603fc00000000 { + compatible = "ibm,xscom", "ibm,power9-xscom"; + ibm,chip-id = <0x0>; + #size-cells = <0x1>; + #address-cells = <0x1>; + reg = <0x603fc 0x0 0x8 0x0>; + + /* PE#0 supports only one stack */ + pbcq@4010c00 { + ibm,pec-index = <0x0>; + reg = <0x4010c00 0x100 0xd010800 0x200>; + compatible = "ibm,power9-pbcq"; + #address-cells = <0x1>; + #size-cells = <0x0>; + + stack@0 { + /* Stack number */ + reg = <0x0>; + /* Chip-scope PHB index */ + ibm,phb-index = <0x0>; + compatible = "ibm,power9-phb-stack"; + status = "okay"; + }; + }; + + /* PE#1 supports two stacks */ + pbcq@4011000 { + ibm,pec-index = <0x1>; + reg = <0x4011000 0x100 0xe010800 0x200>; + compatible = "ibm,power9-pbcq"; + #address-cells = <0x1>; + #size-cells = <0x0>; + + stack@0 { + reg = <0x0>; + ibm,phb-index = <0x1>; + compatible = "ibm,power9-phb-stack"; + status = "okay"; + }; + + stack@1 { + reg = <0x1>; + ibm,phb-index = <0x2>; + compatible = "ibm,power9-phb-stack"; + status = "okay"; + }; + }; + + /* PE#2 supports three stacks */ + pbcq@4011400 { + ibm,pec-index = <0x2>; + reg = <0x4011400 0x100 0xf010800 0x200>; + compatible = "ibm,power9-pbcq"; + #address-cells = <0x1>; + #size-cells = <0x0>; + + stack@0 { + reg = <0x0>; + ibm,phb-index = <0x3>; + compatible = "ibm,power9-phb-stack"; + status = "disabled"; + }; + + stack@1 { + reg = <0x1>; + ibm,phb-index = <0x4>; + compatible = "ibm,power9-phb-stack"; + status = "disabled"; + }; + + stack@2 { + reg = <0x2>; + ibm,phb-index = <0x5>; + compatible = "ibm,power9-phb-stack"; + status = "disabled"; + }; + }; + + chiptod@40000 { + primary; + reg = <0x40000 0x34>; + compatible = "ibm,power-chiptod", "ibm,power9-chiptod"; + }; + + xive@5013400 { + reg = <0x5013000 0x300>; + compatible = "ibm,power9-xive-x"; + }; + + PSI_X0: psihb@5012900 { + reg = <0x5012900 0x100>; + compatible = "ibm,power9-psihb-x", "ibm,psihb-x"; + + /* + * This acts as an interrupt remapper for the 16 + * interrupts coming into the PSI HB. + * OPAL will generate the corresponding interrupt-map + * property with the final XIVE numbers + */ + #interrupt-cells = <0x1>; + #address-cells = <0x0>; + #interrupt-map-mask = <0xff>; + }; + + nx@2010000 { + reg = <0x2010000 0x4000>; + compatible = "ibm,power9-nx"; + }; + }; + + lpcm-opb@6030000000000 { + #address-cells = <0x1>; + #size-cells = <0x1>; + compatible = "ibm,power9-lpcm-opb", "simple-bus"; + ibm,chip-id = <0x0>; + ranges = <0x00000000 0x60300 0x00000000 0x80000000 + 0x80000000 0x60300 0x80000000 0x80000000>; + + opb-master@c0010000 { + compatible = "ibm,power9-lpcm-opb-master"; + reg = <0xc0010000 0x60>; + }; + + opb-arbiter@c0011000 { + compatible = "ibm,power9-lpcm-opb-arbiter"; + reg = <0xc0011000 0x8>; + }; + + lpc-controller@c0012000 { + compatible = "ibm,power9-lpc-controller"; + reg = <0xc0012000 0x100>; + }; + + lpc@f0000000 { + compatible = "ibm,power9-lpc"; + #address-cells = <0x2>; + #size-cells = <0x1>; + ranges = <0x3 0x0 0xf0000000 0x10000000 /* FW space */ + 0x0 0x0 0xe0000000 0x10000000 /* MEM space */ + 0x1 0x0 0xd0010000 0x00010000 /* IO space */ >; + + /* + * We currently only support level interrupts on the LPC, + * we use 1 cell. + */ + #interrupt-cells = <0x1>; + + /* + * Route the LPC interrupts to one of the 4 supported + * PSI interrupt inputs [7...10]. + */ + interrupt-map = <0x0 0x0 0x4 &PSI_X0 0x8 + 0x0 0x0 0xa &PSI_X0 0x9>; + interrupt-map-mask = <0x0 0x0 0xff>; + + /* Devices on the LPC bus go here */ + + serial@i3f8 { + compatible = "ns16550"; + reg = <0x1 0x3f8 0x10>; + current-speed = <0x1c200>; + clock-frequency = <0x1c2000>; + interrupts = <0x4>; + }; + + ipmi@ie4 { + compatible = "ipmi-bt"; + reg = <0x1 0xe4 0x3>; + interrupts = <0x10>; + }; + }; + }; +};