| Message ID | 1532702862-22751-5-git-send-email-arbab@linux.ibm.com |
|---|---|
| State | Superseded |
| Headers | show |
| Series | npu2: Add support for relaxed-ordering mode | expand |
| Context | Check | Description |
|---|---|---|
| snowpatch_ozlabs/apply_patch | success | master/apply_patch Successfully applied |
Reviewed-by: Alistair Popple <alistair@popple.id.au> On Friday, 27 July 2018 9:47:40 AM AEST Reza Arbab wrote: > Add a register offset calculation macro using SM block index, similar to > the other NPU2_*_REG_OFFSET() macros. > > Signed-off-by: Alistair Popple <alistair@popple.id.au> > Signed-off-by: Reza Arbab <arbab@linux.ibm.com> > --- > include/npu2-regs.h | 4 ++++ > 1 file changed, 4 insertions(+) > > diff --git a/include/npu2-regs.h b/include/npu2-regs.h > index d797026..4a17ac8 100644 > --- a/include/npu2-regs.h > +++ b/include/npu2-regs.h > @@ -55,6 +55,10 @@ void npu2_scom_write(uint64_t gcid, uint64_t scom_base, > NPU2_REG_OFFSET(((ndev)->index >> 1), \ > 8 + ((ndev)->index % 2)*2, offset) > > +#define NPU2_SM_REG_OFFSET(ndev, sm, offset) \ > + NPU2_REG_OFFSET(NPU2_STACK_STCK_0 + ((ndev)->index >> 1), \ > + NPU2_BLOCK_SM_0 + (sm), offset) > + > /* Get the offset for this register */ > #define NPU2_REG(reg) \ > ((reg) & 0xffff) >
diff --git a/include/npu2-regs.h b/include/npu2-regs.h index d797026..4a17ac8 100644 --- a/include/npu2-regs.h +++ b/include/npu2-regs.h @@ -55,6 +55,10 @@ void npu2_scom_write(uint64_t gcid, uint64_t scom_base, NPU2_REG_OFFSET(((ndev)->index >> 1), \ 8 + ((ndev)->index % 2)*2, offset) +#define NPU2_SM_REG_OFFSET(ndev, sm, offset) \ + NPU2_REG_OFFSET(NPU2_STACK_STCK_0 + ((ndev)->index >> 1), \ + NPU2_BLOCK_SM_0 + (sm), offset) + /* Get the offset for this register */ #define NPU2_REG(reg) \ ((reg) & 0xffff)