From patchwork Wed Jul 11 02:32:36 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Reza Arbab X-Patchwork-Id: 942298 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [203.11.71.2]) (using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 41QNQW6Hwlz9s00 for ; Wed, 11 Jul 2018 12:32:51 +1000 (AEST) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=linux.ibm.com Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 41QNQW4wBhzDrL9 for ; Wed, 11 Jul 2018 12:32:51 +1000 (AEST) Authentication-Results: lists.ozlabs.org; dmarc=none (p=none dis=none) header.from=linux.ibm.com X-Original-To: skiboot@lists.ozlabs.org Delivered-To: skiboot@lists.ozlabs.org Authentication-Results: lists.ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=linux.ibm.com (client-ip=148.163.158.5; helo=mx0a-001b2d01.pphosted.com; envelope-from=arbab@linux.ibm.com; receiver=) Authentication-Results: lists.ozlabs.org; dmarc=none (p=none dis=none) header.from=linux.ibm.com Received: from mx0a-001b2d01.pphosted.com (mx0b-001b2d01.pphosted.com [148.163.158.5]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 41QNQP1KC5zDr1S for ; Wed, 11 Jul 2018 12:32:44 +1000 (AEST) Received: from pps.filterd (m0098421.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.16.0.22/8.16.0.22) with SMTP id w6B2SR0I116411 for ; Tue, 10 Jul 2018 22:32:42 -0400 Received: from e36.co.us.ibm.com (e36.co.us.ibm.com [32.97.110.154]) by mx0a-001b2d01.pphosted.com with ESMTP id 2k56gnvne6-1 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=NOT) for ; Tue, 10 Jul 2018 22:32:41 -0400 Received: from localhost by e36.co.us.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! 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Violators will be prosecuted; (version=TLSv1/SSLv3 cipher=AES256-GCM-SHA384 bits=256/256) Tue, 10 Jul 2018 20:32:38 -0600 Received: from b03ledav001.gho.boulder.ibm.com (b03ledav001.gho.boulder.ibm.com [9.17.130.232]) by b03cxnp08026.gho.boulder.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id w6B2WbYn10027314 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=FAIL); Tue, 10 Jul 2018 19:32:37 -0700 Received: from b03ledav001.gho.boulder.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id CE1606E050; Tue, 10 Jul 2018 20:32:37 -0600 (MDT) Received: from b03ledav001.gho.boulder.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id B91C76E04C; Tue, 10 Jul 2018 20:32:37 -0600 (MDT) Received: from arbab-laptop.localdomain (unknown [9.53.92.213]) by b03ledav001.gho.boulder.ibm.com (Postfix) with ESMTP; Tue, 10 Jul 2018 20:32:37 -0600 (MDT) Received: by arbab-laptop.localdomain (Postfix, from userid 152845) id 22E724603E1; Tue, 10 Jul 2018 21:32:36 -0500 (CDT) From: Reza Arbab To: skiboot@lists.ozlabs.org Date: Tue, 10 Jul 2018 21:32:36 -0500 X-Mailer: git-send-email 1.8.3.1 X-TM-AS-GCONF: 00 x-cbid: 18071102-0020-0000-0000-00000E3C4AAE X-IBM-SpamModules-Scores: X-IBM-SpamModules-Versions: BY=3.00009347; HX=3.00000241; KW=3.00000007; PH=3.00000004; SC=3.00000266; SDB=6.01059576; UDB=6.00543813; IPR=6.00837497; MB=3.00022094; MTD=3.00000008; XFM=3.00000015; UTC=2018-07-11 02:32:40 X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 18071102-0021-0000-0000-0000623D3197 Message-Id: <1531276356-18469-1-git-send-email-arbab@linux.ibm.com> X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:, , definitions=2018-07-10_09:, , signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 malwarescore=0 suspectscore=1 phishscore=0 bulkscore=0 spamscore=0 clxscore=1015 lowpriorityscore=0 mlxscore=0 impostorscore=0 mlxlogscore=999 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1806210000 definitions=main-1807110023 Subject: [Skiboot] [PATCH] npu2/hw-procedures: Fence bricks via NTL instead of MISC X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.27 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alistair Popple MIME-Version: 1.0 Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" There are a couple of places we can set/unset fence for a brick: 1. MISC register: NPU2_MISC_FENCE_STATE 2. NTL register for the brick: NPU2_NTL_MISC_CFG1(ndev) Recent testing of ATS in combination with GPU reset has exposed a side effect of using (1); if fence is set for all six bricks, it triggers a sticky nmmu latch which prevents the NPU from getting ATR responses. This manifests as a hang in the tests. We have npu2_dev_fence_brick() which uses (1), and only two calls to it. Replace the call which sets fence with a write to (2). Remove the corresponding unset call entirely. It's unneeded because the procedures already do a progression from full fence to half to idle using (2). Signed-off-by: Reza Arbab Reviewed-by: Andrew Donnellan --- hw/npu2-hw-procedures.c | 31 +++++++------------------------ 1 file changed, 7 insertions(+), 24 deletions(-) diff --git a/hw/npu2-hw-procedures.c b/hw/npu2-hw-procedures.c index 7ab08f0..8de6b4d 100644 --- a/hw/npu2-hw-procedures.c +++ b/hw/npu2-hw-procedures.c @@ -236,26 +236,6 @@ static bool poll_fence_status(struct npu2_dev *ndev, uint64_t val) return false; } -static int64_t npu2_dev_fence_brick(struct npu2_dev *ndev, bool set) -{ - /* - * Add support for queisce/fence the brick at - * procedure reset time. - */ - uint32_t brick; - uint64_t val; - - brick = ndev->index; - if (set) - brick += 6; - - val = PPC_BIT(brick); - NPU2DEVINF(ndev, "%s fence brick %d, val %llx\n", set ? "set" : "clear", - ndev->index, val); - npu2_write(ndev->npu, NPU2_MISC_FENCE_STATE, val); - return 0; -} - /* Procedure 1.2.1 - Reset NPU/NDL */ uint32_t reset_ntl(struct npu2_dev *ndev) { @@ -326,9 +306,6 @@ static uint32_t reset_ntl_release(struct npu2_dev *ndev) } - /* Release the fence */ - npu2_dev_fence_brick(ndev, false); - val = npu2_read(ndev->npu, NPU2_NTL_MISC_CFG1(ndev)); val &= 0xFFBFFFFFFFFFFFFF; npu2_write(ndev->npu, NPU2_NTL_MISC_CFG1(ndev), val); @@ -952,7 +929,13 @@ int64_t npu2_dev_procedure(void *dev, struct pci_cfg_reg_filter *pcrf, void npu2_dev_procedure_reset(struct npu2_dev *dev) { - npu2_dev_fence_brick(dev, true); + uint64_t val; + + /* Fence the brick */ + val = npu2_read(dev->npu, NPU2_NTL_MISC_CFG1(dev)); + val |= PPC_BIT(8) | PPC_BIT(9); + npu2_write(dev->npu, NPU2_NTL_MISC_CFG1(dev), val); + npu2_clear_link_flag(dev, NPU2_DEV_DL_RESET); }