From patchwork Mon Jun 19 06:46:47 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gavin Shan X-Patchwork-Id: 777592 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [103.22.144.68]) (using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3wrhNW3g9qz9s76 for ; Mon, 19 Jun 2017 16:47:07 +1000 (AEST) Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 3wrhNW1zRJzDqRW for ; Mon, 19 Jun 2017 16:47:07 +1000 (AEST) X-Original-To: skiboot@lists.ozlabs.org Delivered-To: skiboot@lists.ozlabs.org Received: from mx0a-001b2d01.pphosted.com (mx0a-001b2d01.pphosted.com [148.163.156.1]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 3wrhNL4Q9ZzDq7c for ; Mon, 19 Jun 2017 16:46:58 +1000 (AEST) Received: from pps.filterd (m0098399.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.16.0.20/8.16.0.20) with SMTP id v5J6iug7123371 for ; Mon, 19 Jun 2017 02:46:56 -0400 Received: from e23smtp07.au.ibm.com (e23smtp07.au.ibm.com [202.81.31.140]) by mx0a-001b2d01.pphosted.com with ESMTP id 2b64mrabhd-1 (version=TLSv1.2 cipher=AES256-SHA bits=256 verify=NOT) for ; Mon, 19 Jun 2017 02:46:56 -0400 Received: from localhost by e23smtp07.au.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! 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Violators will be prosecuted; Mon, 19 Jun 2017 16:46:52 +1000 Received: from d23av01.au.ibm.com (d23av01.au.ibm.com [9.190.234.96]) by d23relay06.au.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id v5J6kqDi46071854 for ; Mon, 19 Jun 2017 16:46:52 +1000 Received: from d23av01.au.ibm.com (localhost [127.0.0.1]) by d23av01.au.ibm.com (8.14.4/8.14.4/NCO v10.0 AVout) with ESMTP id v5J6kpXF015901 for ; Mon, 19 Jun 2017 16:46:51 +1000 Received: from ozlabs.au.ibm.com (ozlabs.au.ibm.com [9.192.253.14]) by d23av01.au.ibm.com (8.14.4/8.14.4/NCO v10.0 AVin) with ESMTP id v5J6kp2O015887; Mon, 19 Jun 2017 16:46:51 +1000 Received: from bran.ozlabs.ibm.com (haven.au.ibm.com [9.192.254.114]) by ozlabs.au.ibm.com (Postfix) with ESMTP id 528B6A008E; Mon, 19 Jun 2017 16:46:51 +1000 (AEST) Received: from gwshan.ozlabs.ibm.com (shangw.ozlabs.ibm.com [10.61.2.199]) by bran.ozlabs.ibm.com (Postfix) with ESMTP id 48608E3C84; Mon, 19 Jun 2017 16:46:51 +1000 (AEST) Received: by gwshan.ozlabs.ibm.com (Postfix, from userid 1000) id 3E445AC0DF8; Mon, 19 Jun 2017 16:46:51 +1000 (AEST) From: Gavin Shan To: skiboot@lists.ozlabs.org Date: Mon, 19 Jun 2017 16:46:47 +1000 X-Mailer: git-send-email 2.7.4 In-Reply-To: <1497854809-26032-1-git-send-email-gwshan@linux.vnet.ibm.com> References: <1497854809-26032-1-git-send-email-gwshan@linux.vnet.ibm.com> X-TM-AS-MML: disable x-cbid: 17061906-0044-0000-0000-0000026FA073 X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 17061906-0045-0000-0000-000006FF159F Message-Id: <1497854809-26032-3-git-send-email-gwshan@linux.vnet.ibm.com> X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10432:, , definitions=2017-06-19_05:, , signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 suspectscore=1 malwarescore=0 phishscore=0 adultscore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1703280000 definitions=main-1706190114 Subject: [Skiboot] [PATCH v2 2/4] core/pci: Detach IOV from capability descriptor X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" The IOV struct is associated with the capability descriptor, but it's never used. This detachs IOV struct from the capability descriptor, binds IOV struct with PCI device instead. Signed-off-by: Gavin Shan --- core/pci-iov.c | 3 ++- core/pci.c | 6 +++--- include/pci.h | 15 ++------------- 3 files changed, 7 insertions(+), 17 deletions(-) diff --git a/core/pci-iov.c b/core/pci-iov.c index 9d75b37..627f300 100644 --- a/core/pci-iov.c +++ b/core/pci-iov.c @@ -252,6 +252,7 @@ void pci_init_iov_cap(struct phb *phb, struct pci_device *pd) iov->pd = pd; iov->pos = pos; iov->enabled = false; + pd->iov = iov; pci_iov_update_parameters(iov); - pci_set_cap(pd, PCIECAP_ID_SRIOV, pos, iov, true); + pci_set_cap(pd, PCIECAP_ID_SRIOV, pos, true); } diff --git a/core/pci.c b/core/pci.c index 7cd29fd..1aa906a 100644 --- a/core/pci.c +++ b/core/pci.c @@ -162,7 +162,7 @@ static void pci_init_pcie_cap(struct phb *phb, struct pci_device *pd) return; } - pci_set_cap(pd, PCI_CFG_CAP_ID_EXP, ecap, NULL, false); + pci_set_cap(pd, PCI_CFG_CAP_ID_EXP, ecap, false); /* * XXX We observe a problem on some PLX switches where one @@ -198,7 +198,7 @@ static void pci_init_aer_cap(struct phb *phb, struct pci_device *pd) pos = pci_find_ecap(phb, pd->bdfn, PCIECAP_ID_AER, NULL); if (pos > 0) - pci_set_cap(pd, PCIECAP_ID_AER, pos, NULL, true); + pci_set_cap(pd, PCIECAP_ID_AER, pos, true); } static void pci_init_pm_cap(struct phb *phb, struct pci_device *pd) @@ -207,7 +207,7 @@ static void pci_init_pm_cap(struct phb *phb, struct pci_device *pd) pos = pci_find_cap(phb, pd->bdfn, PCI_CFG_CAP_ID_PM); if (pos > 0) - pci_set_cap(pd, PCI_CFG_CAP_ID_PM, pos, NULL, false); + pci_set_cap(pd, PCI_CFG_CAP_ID_PM, pos, false); } void pci_init_capabilities(struct phb *phb, struct pci_device *pd) diff --git a/include/pci.h b/include/pci.h index f216594..a26a0ea 100644 --- a/include/pci.h +++ b/include/pci.h @@ -79,7 +79,6 @@ struct pci_device { uint64_t cap_list; struct { uint32_t pos; - void *data; } cap[64]; uint32_t mps; /* Max payload size capability */ @@ -87,6 +86,7 @@ struct pci_device { uint32_t pcrf_end; struct list_head pcrf; + struct pci_iov *iov; struct dt_node *dn; struct pci_slot *slot; struct pci_device *parent; @@ -95,17 +95,14 @@ struct pci_device { struct list_node link; }; -static inline void pci_set_cap(struct pci_device *pd, int id, - int pos, void *data, bool ext) +static inline void pci_set_cap(struct pci_device *pd, int id, int pos, bool ext) { if (!ext) { pd->cap_list |= (0x1ul << id); pd->cap[id].pos = pos; - pd->cap[id].data = data; } else { pd->cap_list |= (0x1ul << (id + 32)); pd->cap[id + 32].pos = pos; - pd->cap[id + 32].data = data; } } @@ -127,14 +124,6 @@ static inline int pci_cap(struct pci_device *pd, return pd->cap[id + 32].pos; } -static inline void *pci_cap_data(struct pci_device *pd, int id, bool ext) -{ - if (!ext) - return pd->cap[id].data; - else - return pd->cap[id + 32].data; -} - /* * When generating the device-tree, we need to keep track of * the LSI mapping & swizzle it. This state structure is