From patchwork Tue Nov 22 02:13:10 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Benjamin Herrenschmidt X-Patchwork-Id: 697499 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3tN8KG0Bltz9svs for ; Tue, 22 Nov 2016 13:18:42 +1100 (AEDT) Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 3tN8KF6XzDzDwH8 for ; Tue, 22 Nov 2016 13:18:41 +1100 (AEDT) X-Original-To: skiboot@lists.ozlabs.org Delivered-To: skiboot@lists.ozlabs.org Received: from gate.crashing.org (gate.crashing.org [63.228.1.57]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 3tN8Hx1kGczDwFc for ; Tue, 22 Nov 2016 13:17:32 +1100 (AEDT) Received: from pasglop.ozlabs.ibm.com (localhost.localdomain [127.0.0.1]) by gate.crashing.org (8.14.1/8.13.8) with ESMTP id uAM2DZdI015261; Mon, 21 Nov 2016 20:13:56 -0600 From: Benjamin Herrenschmidt To: skiboot@lists.ozlabs.org Date: Tue, 22 Nov 2016 13:13:10 +1100 Message-Id: <1479780814-6162-8-git-send-email-benh@kernel.crashing.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1479780814-6162-1-git-send-email-benh@kernel.crashing.org> References: <1479780814-6162-1-git-send-email-benh@kernel.crashing.org> Subject: [Skiboot] [PATCH 08/32] xive: Add CPU node "interrupts" properties representing the IPIs X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" This will be used in exploitation mode to request the IPIs for the various threads. Each core node has an "interrupts" property of the standard format for each thread of that core. Signed-off-by: Benjamin Herrenschmidt --- hw/xive.c | 25 +++++++++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/hw/xive.c b/hw/xive.c index 980333b..395cb44 100644 --- a/hw/xive.c +++ b/hw/xive.c @@ -1979,6 +1979,26 @@ static void xive_init_cpu(struct cpu_thread *c) xive_cpu_dbg(c, "CPU IPI is irq %08x\n", xs->ipi_irq); } +static void xive_init_cpu_properties(struct cpu_thread *cpu) +{ + struct cpu_thread *t; + uint32_t iprop[8][2] = { }; + uint32_t i; + + assert(cpu_thread_count <= 8); + + if (!cpu->node) + return; + for (i = 0; i < cpu_thread_count; i++) { + t = (i == 0) ? cpu : find_cpu_by_pir(cpu->pir + i); + if (!t) + continue; + iprop[i][0] = t->xstate->ipi_irq; + iprop[i][1] = 0; /* Edge */ + } + dt_add_property(cpu->node, "interrupts", iprop, cpu_thread_count * 8); + dt_add_property_cells(cpu->node, "interrupt-parent", get_ics_phandle()); +} static uint32_t xive_read_eq(struct xive_cpu_state *xs, bool just_peek) { @@ -2326,6 +2346,11 @@ void init_xive(void) for_each_cpu(cpu) { xive_init_cpu(cpu); } + /* Add interrupts propertie to each CPU node */ + for_each_cpu(cpu) { + if (cpu_is_thread0(cpu)) + xive_init_cpu_properties(cpu); + } /* Calling boot CPU */ xive_cpu_callin(this_cpu());