From patchwork Thu Nov 10 07:34:48 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Benjamin Herrenschmidt X-Patchwork-Id: 693092 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3tDw211QGvz9t1b for ; Thu, 10 Nov 2016 18:40:25 +1100 (AEDT) Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 3tDw206yzdzDvl7 for ; Thu, 10 Nov 2016 18:40:24 +1100 (AEDT) X-Original-To: skiboot@lists.ozlabs.org Delivered-To: skiboot@lists.ozlabs.org Received: from gate.crashing.org (gate.crashing.org [63.228.1.57]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 3tDw0W6FQVzDvgy for ; Thu, 10 Nov 2016 18:39:07 +1100 (AEDT) Received: from pasglop.au.ibm.com (localhost.localdomain [127.0.0.1]) by gate.crashing.org (8.14.1/8.13.8) with ESMTP id uAA7Ysa5030578; Thu, 10 Nov 2016 01:35:22 -0600 From: Benjamin Herrenschmidt To: skiboot@lists.ozlabs.org Date: Thu, 10 Nov 2016 18:34:48 +1100 Message-Id: <1478763292-23238-12-git-send-email-benh@kernel.crashing.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1478763292-23238-1-git-send-email-benh@kernel.crashing.org> References: <1478763292-23238-1-git-send-email-benh@kernel.crashing.org> Subject: [Skiboot] [PATCH 12/16] xive: Fix IPI EOI logic in opal_xive_eoi() X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" We only want to directly EOI the interrupt used to emulate the MFRR, for all the other "IPI" (aka XIVE produced interrupts), we want to go via the normal source mechanism. Signed-off-by: Benjamin Herrenschmidt --- hw/xive.c | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/hw/xive.c b/hw/xive.c index 69b5738..1237cd9 100644 --- a/hw/xive.c +++ b/hw/xive.c @@ -331,7 +331,7 @@ struct xive { * potentially handle more than one block per chip in the future. */ uint32_t int_hw_bot; /* Bottom of HW allocation */ - uint32_t int_ipi_top; /* Highest IPI handed out so far */ + uint32_t int_ipi_top; /* Highest IPI handed out so far + 1 */ /* Embedded source IPIs */ struct xive_src ipis; @@ -1995,25 +1995,25 @@ static int64_t opal_xive_eoi(uint32_t xirr) } #endif - /* Perform source level EOI if it's a HW interrupt, otherwise, - * EOI ourselves + /* Perform source level EOI if it's not our emulated MFRR IPI + * otherwise EOI ourselves */ src_x = xive_from_isn(isn); if (src_x) { uint32_t idx = GIRQ_TO_IDX(isn); /* Is it an IPI ? */ - if (idx < src_x->int_ipi_top) { - xive_vdbg(src_x, "EOI of IDX %x in IPI range\n", idx); + if (special_ipi) { xive_ipi_eoi(src_x, idx); - /* It was a special IPI, check mfrr and eventually - * re-trigger. We check against the new CPPR since - * we are about to update the HW. + /* Check mfrr and eventually re-trigger. We check + * against the new CPPR since we are about to update + * the HW. */ - if (special_ipi && xs->mfrr < cppr) + if (xs->mfrr < cppr) xive_ipi_trigger(src_x, idx); } else { + /* Otherwise go through the source mechanism */ xive_vdbg(src_x, "EOI of IDX %x in EXT range\n", idx); irq_source_eoi(isn); }