From patchwork Thu Nov 10 07:34:46 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Benjamin Herrenschmidt X-Patchwork-Id: 693091 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3tDw1l2lkCz9t1b for ; Thu, 10 Nov 2016 18:40:11 +1100 (AEDT) Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 3tDw1l21WPzDvkW for ; Thu, 10 Nov 2016 18:40:11 +1100 (AEDT) X-Original-To: skiboot@lists.ozlabs.org Delivered-To: skiboot@lists.ozlabs.org Received: from gate.crashing.org (gate.crashing.org [63.228.1.57]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 3tDw0V2BdPzDvhY for ; Thu, 10 Nov 2016 18:39:06 +1100 (AEDT) Received: from pasglop.au.ibm.com (localhost.localdomain [127.0.0.1]) by gate.crashing.org (8.14.1/8.13.8) with ESMTP id uAA7Ysa3030578; Thu, 10 Nov 2016 01:35:18 -0600 From: Benjamin Herrenschmidt To: skiboot@lists.ozlabs.org Date: Thu, 10 Nov 2016 18:34:46 +1100 Message-Id: <1478763292-23238-10-git-send-email-benh@kernel.crashing.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1478763292-23238-1-git-send-email-benh@kernel.crashing.org> References: <1478763292-23238-1-git-send-email-benh@kernel.crashing.org> Subject: [Skiboot] [PATCH 10/16] xive: Fix comments in xive_source_set_xive() X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" Properly documenting assumptions and behaviour related to interrupts occurring while masked. This reflects the documentation update. Signed-off-by: Benjamin Herrenschmidt --- hw/xive.c | 22 ++++++++++++++++------ 1 file changed, 16 insertions(+), 6 deletions(-) diff --git a/hw/xive.c b/hw/xive.c index 3759049..33c8fe2 100644 --- a/hw/xive.c +++ b/hw/xive.c @@ -1525,6 +1525,21 @@ static int64_t xive_source_set_xive(struct irq_source *is, uint32_t isn, uint32_t idx = isn - s->esb_base; void *mmio_base; + /* + * WARNING: There is an inherent race with the use of the + * mask bit in the EAS/IVT. When masked, interrupts are "lost" + * but their P/Q bits are still set. So when unmasking, one has + * to check the P bit and possibly trigger a resend. + * + * We "deal" with it by relying on the fact that the OS will + * lazy disable MSIs. Thus mask will only be called if the + * interrupt occurred while already logically masked. Thus + * losing subsequent occurrences is of no consequences, we just + * need to "cleanup" P and Q when unmasking. + * + * This needs to be documented in the OPAL APIs + */ + /* Unmangle server */ server >>= 2; @@ -1532,12 +1547,7 @@ static int64_t xive_source_set_xive(struct irq_source *is, uint32_t isn, if (!xive_set_eq_info(isn, server, prio)) return OPAL_PARAMETER; - /* Ensure it's enabled/disabled in the source controller. - * - * This won't do much for LSIs but will work for MSIs and will - * ensure that a stray P bit left over won't block further - * interrupts when enabling - */ + /* Ensure it's enabled/disabled in the source controller */ mmio_base = s->esb_mmio + (1ul << s->esb_shift) * idx; if (s->flags & XIVE_SRC_EOI_PAGE1) mmio_base += 1ull << (s->esb_shift - 1);