From patchwork Fri Sep 16 04:52:12 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Benjamin Herrenschmidt X-Patchwork-Id: 670680 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3sb5xh3stHz9rxl for ; Fri, 16 Sep 2016 17:09:28 +1000 (AEST) Received: from ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 3sb5xh377HzDscC for ; Fri, 16 Sep 2016 17:09:28 +1000 (AEST) X-Original-To: skiboot@lists.ozlabs.org Delivered-To: skiboot@lists.ozlabs.org Received: from gate.crashing.org (gate.crashing.org [63.228.1.57]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 3sb2zv3dDqzDsZQ for ; Fri, 16 Sep 2016 14:56:11 +1000 (AEST) Received: from pasglop.ozlabs.ibm.com (localhost.localdomain [127.0.0.1]) by gate.crashing.org (8.14.1/8.13.8) with ESMTP id u8G4qMSl028383; Thu, 15 Sep 2016 23:52:33 -0500 From: Benjamin Herrenschmidt To: skiboot@lists.ozlabs.org Date: Fri, 16 Sep 2016 14:52:12 +1000 Message-Id: <1474001535-16780-8-git-send-email-benh@kernel.crashing.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1474001535-16780-1-git-send-email-benh@kernel.crashing.org> References: <1474001535-16780-1-git-send-email-benh@kernel.crashing.org> Subject: [Skiboot] [PATCH 08/11] xive: Fix IPI EOI logic in opal_xive_eoi() X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" We only want to directly EOI the interrupt used to emulate the MFRR, for all the other "IPI" (aka XIVE produced interrupts), we want to go via the normal source mechanism. Signed-off-by: Benjamin Herrenschmidt --- hw/xive.c | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/hw/xive.c b/hw/xive.c index 69b5738..1237cd9 100644 --- a/hw/xive.c +++ b/hw/xive.c @@ -331,7 +331,7 @@ struct xive { * potentially handle more than one block per chip in the future. */ uint32_t int_hw_bot; /* Bottom of HW allocation */ - uint32_t int_ipi_top; /* Highest IPI handed out so far */ + uint32_t int_ipi_top; /* Highest IPI handed out so far + 1 */ /* Embedded source IPIs */ struct xive_src ipis; @@ -1995,25 +1995,25 @@ static int64_t opal_xive_eoi(uint32_t xirr) } #endif - /* Perform source level EOI if it's a HW interrupt, otherwise, - * EOI ourselves + /* Perform source level EOI if it's not our emulated MFRR IPI + * otherwise EOI ourselves */ src_x = xive_from_isn(isn); if (src_x) { uint32_t idx = GIRQ_TO_IDX(isn); /* Is it an IPI ? */ - if (idx < src_x->int_ipi_top) { - xive_vdbg(src_x, "EOI of IDX %x in IPI range\n", idx); + if (special_ipi) { xive_ipi_eoi(src_x, idx); - /* It was a special IPI, check mfrr and eventually - * re-trigger. We check against the new CPPR since - * we are about to update the HW. + /* Check mfrr and eventually re-trigger. We check + * against the new CPPR since we are about to update + * the HW. */ - if (special_ipi && xs->mfrr < cppr) + if (xs->mfrr < cppr) xive_ipi_trigger(src_x, idx); } else { + /* Otherwise go through the source mechanism */ xive_vdbg(src_x, "EOI of IDX %x in EXT range\n", idx); irq_source_eoi(isn); }