From patchwork Fri Sep 16 04:52:06 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Benjamin Herrenschmidt X-Patchwork-Id: 670676 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3sb5x31bZ0z9rxl for ; Fri, 16 Sep 2016 17:08:55 +1000 (AEST) Received: from ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 3sb5x30HHPzDsfC for ; Fri, 16 Sep 2016 17:08:55 +1000 (AEST) X-Original-To: skiboot@lists.ozlabs.org Delivered-To: skiboot@lists.ozlabs.org Received: from gate.crashing.org (gate.crashing.org [63.228.1.57]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 3sb2zh1mG3zDsZM for ; Fri, 16 Sep 2016 14:55:59 +1000 (AEST) Received: from pasglop.ozlabs.ibm.com (localhost.localdomain [127.0.0.1]) by gate.crashing.org (8.14.1/8.13.8) with ESMTP id u8G4qMSf028383; Thu, 15 Sep 2016 23:52:25 -0500 From: Benjamin Herrenschmidt To: skiboot@lists.ozlabs.org Date: Fri, 16 Sep 2016 14:52:06 +1000 Message-Id: <1474001535-16780-2-git-send-email-benh@kernel.crashing.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1474001535-16780-1-git-send-email-benh@kernel.crashing.org> References: <1474001535-16780-1-git-send-email-benh@kernel.crashing.org> Subject: [Skiboot] [PATCH 02/11] xive: Fix mangling of interrupt server# in opal_get/set_xive() X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" The OPAL API uses mangled server numbers with the link in the bottom 2 bits like a real XICS does, we need to account for it. Signed-off-by: Benjamin Herrenschmidt --- hw/xive.c | 12 +++++------- 1 file changed, 5 insertions(+), 7 deletions(-) diff --git a/hw/xive.c b/hw/xive.c index 3c25cae..ba32925 100644 --- a/hw/xive.c +++ b/hw/xive.c @@ -1477,7 +1477,7 @@ static int64_t xive_source_get_xive(struct irq_source *is __unused, uint32_t target_id; if (xive_get_eq_info(isn, &target_id, prio)) { - *server = target_id; + *server = target_id << 2; return OPAL_SUCCESS; } else return OPAL_PARAMETER; @@ -1490,6 +1490,9 @@ static int64_t xive_source_set_xive(struct irq_source *is, uint32_t isn, uint32_t idx = isn - s->esb_base; void *mmio_base; + /* Unmangle server */ + server >>= 2; + /* Let XIVE configure the EQ */ if (!xive_set_eq_info(isn, server, prio)) return OPAL_PARAMETER; @@ -1704,15 +1707,10 @@ struct xive_cpu_state { static void xive_ipi_init(struct xive *x, struct cpu_thread *cpu) { struct xive_cpu_state *xs = cpu->xstate; - uint32_t idx = GIRQ_TO_IDX(xs->ipi_irq); - uint8_t *mm = x->esb_mmio + idx * 0x20000; assert(xs); - xive_source_set_xive(&x->ipis.is, xs->ipi_irq, cpu->pir, 0x7); - - /* Clear P and Q */ - in_8(mm + 0x10c00); + xive_source_set_xive(&x->ipis.is, xs->ipi_irq, cpu->pir << 2, 0x7); } static void xive_ipi_eoi(struct xive *x, uint32_t idx)