From patchwork Fri Sep 16 04:50:37 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Benjamin Herrenschmidt X-Patchwork-Id: 670671 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3sb5w66WYWz9sD6 for ; Fri, 16 Sep 2016 17:08:06 +1000 (AEST) Received: from ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 3sb5w65ghNzDshS for ; Fri, 16 Sep 2016 17:08:06 +1000 (AEST) X-Original-To: skiboot@lists.ozlabs.org Delivered-To: skiboot@lists.ozlabs.org Received: from gate.crashing.org (gate.crashing.org [63.228.1.57]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 3sb2xn2JHpzDsZM for ; Fri, 16 Sep 2016 14:54:21 +1000 (AEST) Received: from pasglop.ozlabs.ibm.com (localhost.localdomain [127.0.0.1]) by gate.crashing.org (8.14.1/8.13.8) with ESMTP id u8G4oj39028322; Thu, 15 Sep 2016 23:50:46 -0500 From: Benjamin Herrenschmidt To: skiboot@lists.ozlabs.org Date: Fri, 16 Sep 2016 14:50:37 +1000 Message-Id: <1474001440-15953-1-git-send-email-benh@kernel.crashing.org> X-Mailer: git-send-email 2.7.4 Subject: [Skiboot] [PATCH 1/4] psi: Add DT option to disable LPC interrupts X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" Some sim models have the LPC interrupts stuck asserted on secondary chips so we add a device-tree option that makes us set the policy for these to "Linux" instead of "OPAL". Since they aren't referenced in the device-tree this will de-facto prevent them from being enabled Signed-off-by: Benjamin Herrenschmidt --- hw/psi.c | 21 +++++++++++++++++++++ include/psi.h | 1 + 2 files changed, 22 insertions(+) diff --git a/hw/psi.c b/hw/psi.c index 900886a..63a64d0 100644 --- a/hw/psi.c +++ b/hw/psi.c @@ -539,6 +539,9 @@ static uint64_t psi_p8_irq_attributes(struct irq_source *is, uint32_t isn) uint32_t idx = isn - psi->interrupt; uint64_t attr; + if (psi->no_lpc_irqs && idx == P8_IRQ_PSI_LPC) + return IRQ_ATTR_TARGET_LINUX; + if (idx == P8_IRQ_PSI_EXTERNAL && psi_ext_irq_policy == EXTERNAL_IRQ_POLICY_LINUX) return IRQ_ATTR_TARGET_LINUX; @@ -606,6 +609,21 @@ static void psihb_p9_interrupt(struct irq_source *is, uint32_t isn) static uint64_t psi_p9_irq_attributes(struct irq_source *is __unused, uint32_t isn __unused) { + struct psi *psi = is->data; + unsigned int idx = isn & 0xf; + + /* If LPC interrupts are disabled, route them to Linux + * (who will not request them since they aren't referenced + * in the device tree) + */ + if (psi->no_lpc_irqs && + (idx == P9_PSI_IRQ_LPC_SIRQ0 || + idx == P9_PSI_IRQ_LPC_SIRQ1 || + idx == P9_PSI_IRQ_LPC_SIRQ2 || + idx == P9_PSI_IRQ_LPC_SIRQ3 || + idx == P9_PSI_IRQ_LPCHC)) + return IRQ_ATTR_TARGET_LINUX; + /* XXX For now, all go to OPAL, this will change */ return IRQ_ATTR_TARGET_OPAL | IRQ_ATTR_TARGET_FREQUENT; } @@ -1020,6 +1038,9 @@ static bool psi_init_psihb(struct dt_node *psihb) } chip->psi = psi; + if (dt_has_node_property(psihb, "no-lpc-interrupts", NULL)) + psi->no_lpc_irqs = true; + psi_activate_phb(psi); psi_init_interrupts(psi); psi_create_mm_dtnode(psi); diff --git a/include/psi.h b/include/psi.h index 24d4206..5982adc 100644 --- a/include/psi.h +++ b/include/psi.h @@ -245,6 +245,7 @@ struct psi { unsigned int chip_id; unsigned int interrupt; bool active; + bool no_lpc_irqs; }; extern void psi_set_link_polling(bool active);