From patchwork Fri Jun 24 22:47:48 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Benjamin Herrenschmidt X-Patchwork-Id: 640480 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3rbtqk362zz9s9N for ; Sat, 25 Jun 2016 08:51:46 +1000 (AEST) Received: from ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 3rbtqk2MgzzDqvL for ; Sat, 25 Jun 2016 08:51:46 +1000 (AEST) X-Original-To: skiboot@lists.ozlabs.org Delivered-To: skiboot@lists.ozlabs.org Received: from gate.crashing.org (gate.crashing.org [63.228.1.57]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 3rbtn91B95zDqnV for ; Sat, 25 Jun 2016 08:49:32 +1000 (AEST) Received: from pasglop.au.ibm.com (localhost.localdomain [127.0.0.1]) by gate.crashing.org (8.14.1/8.13.8) with ESMTP id u5OMm2N0022384; Fri, 24 Jun 2016 17:49:05 -0500 From: Benjamin Herrenschmidt To: skiboot@lists.ozlabs.org Date: Sat, 25 Jun 2016 08:47:48 +1000 Message-Id: <1466808476-32690-25-git-send-email-benh@kernel.crashing.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1466808476-32690-1-git-send-email-benh@kernel.crashing.org> References: <1466808476-32690-1-git-send-email-benh@kernel.crashing.org> Subject: [Skiboot] [PATCH 25/33] Move around comment in interrupts.h X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" Signed-off-by: Benjamin Herrenschmidt --- include/interrupts.h | 66 ++++++++++++++++++++++++++-------------------------- 1 file changed, 33 insertions(+), 33 deletions(-) diff --git a/include/interrupts.h b/include/interrupts.h index 19f542f..0380c59 100644 --- a/include/interrupts.h +++ b/include/interrupts.h @@ -181,38 +181,6 @@ * */ -/* Note about interrupt numbers on P9 - * ================================== - * - * P9 uses a completely different interrupt controller, XIVE. - * - * It targets objects using a combination of block number and - * index within a block. However, we try to avoid exposing that - * split to the OS in order to keep some abstraction in case the - * way we allocate these change. - * - * The lowest level entity in Xive is the EST (state bit array). - * - * Those are spread between PHBs, PSI bridge and XIVE itself which - * provide a large amount of state bits for IPIs and other SW and HW - * generated interrupts by sources that don't have their own ESB logic - * - * Due to that spread, they aren't a good representation of a global - * interrupt number. - * - * Each such source however needs to be targetted at an EAS (IVT) - * entry in a table which will control targetting information and - * associate that interrupt with a logical number. - * - * Thus that table entry number represents a good "global interrupt - * number". Additionally, for the host OS, we will keep the logical - * number equal to the global number. - * - * The details of how these are assigned on P9 can be found in - * hw/xive.c. P9 HW will generally not use the definitions and - * functions in this file (or the corresponding core/interrupts.c). - */ - uint32_t p8_chip_irq_block_base(uint32_t chip, uint32_t block); uint32_t p8_chip_irq_phb_base(uint32_t chip, uint32_t phb); uint32_t p8_irq_to_chip(uint32_t irq); @@ -249,12 +217,43 @@ uint32_t p8_irq_to_phb(uint32_t irq); #define P8_IRQ_PSI_LOCAL_COUNT 5 #define P8_IRQ_PSI_ALL_COUNT 6 +/* TBD: NX, AS, ... + */ /* These are passed onto Linux */ #define P8_IRQ_PSI_LINUX_BASE 5 #define P8_IRQ_PSI_HOST_ERR 5 /* Used for UART */ #define P8_IRQ_PSI_LINUX_COUNT 1 -/* TBD: NX, AS, ... +/* Note about interrupt numbers on P9 + * ================================== + * + * P9 uses a completely different interrupt controller, XIVE. + * + * It targets objects using a combination of block number and + * index within a block. However, we try to avoid exposing that + * split to the OS in order to keep some abstraction in case the + * way we allocate these change. + * + * The lowest level entity in Xive is the ESB (state bits). + * + * Those are spread between PHBs, PSI bridge and XIVE itself which + * provide a large amount of state bits for IPIs and other SW and HW + * generated interrupts by sources that don't have their own ESB logic + * + * Due to that spread, they aren't a good representation of a global + * interrupt number. + * + * Each such source however needs to be targetted at an EAS (IVT) + * entry in a table which will control targetting information and + * associate that interrupt with a logical number. + * + * Thus that table entry number represents a good "global interrupt + * number". Additionally, for the host OS, we will keep the logical + * number equal to the global number. + * + * The details of how these are assigned on P9 can be found in + * hw/xive.c. P9 HW will only use a subset of the definitions and + * functions in this file (or the corresponding core/interrupts.c). */ /* @@ -299,3 +298,4 @@ extern bool irq_source_eoi(uint32_t isn); #endif /* __INTERRUPTS_H */ +