From patchwork Fri Jun 24 22:47:45 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Benjamin Herrenschmidt X-Patchwork-Id: 640477 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [103.22.144.68]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3rbtq83svXz9sp7 for ; Sat, 25 Jun 2016 08:51:16 +1000 (AEST) Received: from ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 3rbtq836xdzDqpR for ; Sat, 25 Jun 2016 08:51:16 +1000 (AEST) X-Original-To: skiboot@lists.ozlabs.org Delivered-To: skiboot@lists.ozlabs.org Received: from gate.crashing.org (gate.crashing.org [63.228.1.57]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 3rbtmb5bXTzDqlf for ; Sat, 25 Jun 2016 08:49:03 +1000 (AEST) Received: from pasglop.au.ibm.com (localhost.localdomain [127.0.0.1]) by gate.crashing.org (8.14.1/8.13.8) with ESMTP id u5OMm2Mv022384; Fri, 24 Jun 2016 17:48:58 -0500 From: Benjamin Herrenschmidt To: skiboot@lists.ozlabs.org Date: Sat, 25 Jun 2016 08:47:45 +1000 Message-Id: <1466808476-32690-22-git-send-email-benh@kernel.crashing.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1466808476-32690-1-git-send-email-benh@kernel.crashing.org> References: <1466808476-32690-1-git-send-email-benh@kernel.crashing.org> Subject: [Skiboot] [PATCH 22/33] interrupts: LPC is always an interrupt controller X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" Whether we have Naples or not, the "interrupts" properties of the child of the LPC node are always in the LPC interrupt number space, and so should always have the LPC controller as their interrupt controller. Signed-off-by: Benjamin Herrenschmidt --- hw/lpc.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/hw/lpc.c b/hw/lpc.c index 6c40786..083a5af 100644 --- a/hw/lpc.c +++ b/hw/lpc.c @@ -813,8 +813,9 @@ static void lpc_init_chip_p8(struct dt_node *xn) printf("LPC: Bus on chip %d, access via XSCOM, PCB_Addr=0x%x\n", chip->id, chip->lpc_xbase); lpc_init_interrupts(chip); - if (chip->type == PROC_CHIP_P8_NAPLES) - dt_add_property(xn, "interrupt-controller", NULL, 0); + dt_add_property(xn, "interrupt-controller", NULL, 0); + dt_add_property_cells(xn, "#interrupt-cells", 1); + assert(dt_prop_get_u32(xn, "#address-cells") == 2); } static void lpc_init_chip_p9(struct dt_node *opb_node)