From patchwork Fri Jun 10 05:03:38 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gavin Shan X-Patchwork-Id: 633505 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [103.22.144.68]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3rQqrD5qw6z9sD3 for ; Fri, 10 Jun 2016 15:05:48 +1000 (AEST) Received: from ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 3rQqrD4ZdlzDqP9 for ; Fri, 10 Jun 2016 15:05:48 +1000 (AEST) X-Original-To: skiboot@lists.ozlabs.org Delivered-To: skiboot@lists.ozlabs.org Received: from mx0a-001b2d01.pphosted.com (mx0a-001b2d01.pphosted.com [148.163.156.1]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 3rQqqP3wCxzDqJ1 for ; Fri, 10 Jun 2016 15:05:05 +1000 (AEST) Received: from pps.filterd (m0098399.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.16.0.11/8.16.0.11) with SMTP id u5A53nXn067577 for ; Fri, 10 Jun 2016 01:05:03 -0400 Received: from e23smtp07.au.ibm.com (e23smtp07.au.ibm.com [202.81.31.140]) by mx0a-001b2d01.pphosted.com with ESMTP id 23e9m55txp-1 (version=TLSv1.2 cipher=AES256-SHA bits=256 verify=NOT) for ; Fri, 10 Jun 2016 01:05:03 -0400 Received: from localhost by e23smtp07.au.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! 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Violators will be prosecuted; Fri, 10 Jun 2016 15:04:59 +1000 X-IBM-Helo: d23dlp02.au.ibm.com X-IBM-MailFrom: gwshan@linux.vnet.ibm.com X-IBM-RcptTo: skiboot@lists.ozlabs.org Received: from d23relay06.au.ibm.com (d23relay06.au.ibm.com [9.185.63.219]) by d23dlp02.au.ibm.com (Postfix) with ESMTP id 8B8B02BB0064 for ; Fri, 10 Jun 2016 15:04:48 +1000 (EST) Received: from d23av02.au.ibm.com (d23av02.au.ibm.com [9.190.235.138]) by d23relay06.au.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id u5A54h9v43646978 for ; Fri, 10 Jun 2016 15:04:43 +1000 Received: from d23av02.au.ibm.com (localhost [127.0.0.1]) by d23av02.au.ibm.com (8.14.4/8.14.4/NCO v10.0 AVout) with ESMTP id u5A54bw2024812 for ; Fri, 10 Jun 2016 15:04:38 +1000 Received: from ozlabs.au.ibm.com (ozlabs.au.ibm.com [9.192.253.14]) by d23av02.au.ibm.com (8.14.4/8.14.4/NCO v10.0 AVin) with ESMTP id u5A54bQi024687; Fri, 10 Jun 2016 15:04:37 +1000 Received: from bran.ozlabs.ibm.com (haven.au.ibm.com [9.192.254.114]) by ozlabs.au.ibm.com (Postfix) with ESMTP id 40EABA0199; Fri, 10 Jun 2016 15:03:57 +1000 (AEST) Received: from gwshan (shangw.ozlabs.ibm.com [10.61.2.199]) by bran.ozlabs.ibm.com (Postfix) with ESMTP id 3F206E3B1A; Fri, 10 Jun 2016 15:03:57 +1000 (AEST) Received: by gwshan (Postfix, from userid 1000) id 24EF4942CA3; Fri, 10 Jun 2016 15:03:57 +1000 (AEST) From: Gavin Shan To: skiboot@lists.ozlabs.org Date: Fri, 10 Jun 2016 15:03:38 +1000 X-Mailer: git-send-email 2.1.0 In-Reply-To: <1465535032-26749-1-git-send-email-gwshan@linux.vnet.ibm.com> References: <1465535032-26749-1-git-send-email-gwshan@linux.vnet.ibm.com> X-TM-AS-MML: disable X-Content-Scanned: Fidelis XPS MAILER x-cbid: 16061005-0044-0000-0000-000001B2CACA X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 16061005-0045-0000-0000-000004E7256B Message-Id: <1465535032-26749-10-git-send-email-gwshan@linux.vnet.ibm.com> X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10432:, , definitions=2016-06-10_04:, , signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 suspectscore=1 malwarescore=0 phishscore=0 adultscore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1604210000 definitions=main-1606100058 Subject: [Skiboot] [PATCH v12 09/23] core/pci: Fix wrong reserved PE# in enumeration X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair@popple.id.au MIME-Version: 1.0 Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" When scanning to non-existing PCI device, EEH (frozen) error is usually happening. We clear the unexpected frozen PE state after it. The reserved PE number is assumed to be 0 wrongly. So the frozen state on the reserved PE number isn't cleared properly. This introduces struct phb_ops::get_reserved_pe_number() to retrieve the reserved PE number from platforms. Then the EEH frozen state checking and clearing are applied to the reserved PE number. Signed-off-by: Gavin Shan --- core/pci.c | 15 ++++++++++++--- hw/npu.c | 1 + hw/p7ioc-phb.c | 6 ++++++ hw/phb3.c | 6 ++++++ include/pci.h | 1 + 5 files changed, 26 insertions(+), 3 deletions(-) diff --git a/core/pci.c b/core/pci.c index 9b238d0..3d4f639 100644 --- a/core/pci.c +++ b/core/pci.c @@ -274,11 +274,19 @@ static struct pci_device *pci_scan_one(struct phb *phb, struct pci_device *paren */ static void pci_check_clear_freeze(struct phb *phb) { - int64_t rc; uint8_t freeze_state; uint16_t pci_error_type, sev; + int64_t pe_number, rc; + + /* Retrieve the reserved PE number */ + pe_number = OPAL_PARAMETER; + if (phb->ops->get_reserved_pe_number) + pe_number = phb->ops->get_reserved_pe_number(); + if (pe_number < 0) + return; - rc = phb->ops->eeh_freeze_status(phb, 0, &freeze_state, + /* Retrieve the frozen state */ + rc = phb->ops->eeh_freeze_status(phb, pe_number, &freeze_state, &pci_error_type, &sev, NULL); if (rc) return; @@ -290,7 +298,8 @@ static void pci_check_clear_freeze(struct phb *phb) PCIERR(phb, 0, "Fatal probe in %s error !\n", __func__); return; } - phb->ops->eeh_freeze_clear(phb, 0, OPAL_EEH_ACTION_CLEAR_FREEZE_ALL); + phb->ops->eeh_freeze_clear(phb, pe_number, + OPAL_EEH_ACTION_CLEAR_FREEZE_ALL); } /* pci_enable_bridge - Called before scanning a bridge diff --git a/hw/npu.c b/hw/npu.c index 79b232a..a8f9f06 100644 --- a/hw/npu.c +++ b/hw/npu.c @@ -1103,6 +1103,7 @@ static const struct phb_ops npu_ops = { .cfg_write16 = npu_dev_cfg_write16, .cfg_write32 = npu_dev_cfg_write32, .choose_bus = NULL, + .get_reserved_pe_number = NULL, .device_init = NULL, .phb_final_fixup = npu_phb_final_fixup, .presence_detect = NULL, diff --git a/hw/p7ioc-phb.c b/hw/p7ioc-phb.c index bad7d0a..591c9ec 100644 --- a/hw/p7ioc-phb.c +++ b/hw/p7ioc-phb.c @@ -2304,6 +2304,11 @@ static uint8_t p7ioc_choose_bus(struct phb *phb __unused, return al; } +static int64_t p7ioc_get_reserved_pe_number(void) +{ + return 127; +} + /* p7ioc_phb_init_ioda_cache - Reset the IODA cache values */ static void p7ioc_phb_init_ioda_cache(struct p7ioc_phb *p) @@ -2558,6 +2563,7 @@ static const struct phb_ops p7ioc_phb_ops = { .cfg_write16 = p7ioc_pcicfg_write16, .cfg_write32 = p7ioc_pcicfg_write32, .choose_bus = p7ioc_choose_bus, + .get_reserved_pe_number = p7ioc_get_reserved_pe_number, .device_init = p7ioc_device_init, .pci_reinit = p7ioc_pci_reinit, .eeh_freeze_status = p7ioc_eeh_freeze_status, diff --git a/hw/phb3.c b/hw/phb3.c index ab9d117..ab6922c 100644 --- a/hw/phb3.c +++ b/hw/phb3.c @@ -295,6 +295,11 @@ static uint8_t phb3_choose_bus(struct phb *phb __unused, return candidate; } +static int64_t phb3_get_reserved_pe_number(void) +{ + return PHB3_RESERVED_PE_NUM; +} + static void phb3_root_port_init(struct phb *phb, struct pci_device *dev, int ecap, int aercap) { @@ -3580,6 +3585,7 @@ static const struct phb_ops phb3_ops = { .cfg_write16 = phb3_pcicfg_write16, .cfg_write32 = phb3_pcicfg_write32, .choose_bus = phb3_choose_bus, + .get_reserved_pe_number = phb3_get_reserved_pe_number, .device_init = phb3_device_init, .presence_detect = phb3_presence_detect, .ioda_reset = phb3_ioda_reset, diff --git a/include/pci.h b/include/pci.h index aec4808..bd966ba 100644 --- a/include/pci.h +++ b/include/pci.h @@ -254,6 +254,7 @@ struct phb_ops { uint8_t (*choose_bus)(struct phb *phb, struct pci_device *bridge, uint8_t candidate, uint8_t *max_bus, bool *use_max); + int64_t (*get_reserved_pe_number)(void); /* * Device init method is called after a device has been detected