From patchwork Fri May 20 06:32:18 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gavin Shan X-Patchwork-Id: 624321 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3r9ypF3FLnz9t3h for ; Fri, 20 May 2016 16:34:29 +1000 (AEST) Received: from ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 3r9ypF2KnkzDqHm for ; Fri, 20 May 2016 16:34:29 +1000 (AEST) X-Original-To: skiboot@lists.ozlabs.org Delivered-To: skiboot@lists.ozlabs.org Received: from e23smtp01.au.ibm.com (e23smtp01.au.ibm.com [202.81.31.143]) (using TLSv1.2 with cipher CAMELLIA256-SHA (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 3r9ynL1hT3zDqDv for ; Fri, 20 May 2016 16:33:42 +1000 (AEST) Received: from localhost by e23smtp01.au.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! 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Violators will be prosecuted; Fri, 20 May 2016 16:33:40 +1000 X-IBM-Helo: d23dlp02.au.ibm.com X-IBM-MailFrom: gwshan@linux.vnet.ibm.com X-IBM-RcptTo: skiboot@lists.ozlabs.org Received: from d23relay09.au.ibm.com (d23relay09.au.ibm.com [9.185.63.181]) by d23dlp02.au.ibm.com (Postfix) with ESMTP id 0510F2BB0054 for ; Fri, 20 May 2016 16:33:39 +1000 (EST) Received: from d23av02.au.ibm.com (d23av02.au.ibm.com [9.190.235.138]) by d23relay09.au.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id u4K6XUXE60293242 for ; Fri, 20 May 2016 16:33:38 +1000 Received: from d23av02.au.ibm.com (localhost [127.0.0.1]) by d23av02.au.ibm.com (8.14.4/8.14.4/NCO v10.0 AVout) with ESMTP id u4K6X6DR014837 for ; Fri, 20 May 2016 16:33:06 +1000 Received: from ozlabs.au.ibm.com (ozlabs.au.ibm.com [9.192.253.14]) by d23av02.au.ibm.com (8.14.4/8.14.4/NCO v10.0 AVin) with ESMTP id u4K6X58Z014216; Fri, 20 May 2016 16:33:06 +1000 Received: from bran.ozlabs.ibm.com (haven.au.ibm.com [9.192.254.114]) by ozlabs.au.ibm.com (Postfix) with ESMTP id 1DC7DA03BE; Fri, 20 May 2016 16:32:33 +1000 (AEST) Received: from gwshan (shangw.ozlabs.ibm.com [10.61.2.199]) by bran.ozlabs.ibm.com (Postfix) with ESMTP id 266DBE3A8D; Fri, 20 May 2016 16:32:33 +1000 (AEST) Received: by gwshan (Postfix, from userid 1000) id 029B0942543; Fri, 20 May 2016 16:32:32 +1000 (AEST) From: Gavin Shan To: skiboot@lists.ozlabs.org Date: Fri, 20 May 2016 16:32:18 +1000 Message-Id: <1463725945-12916-17-git-send-email-gwshan@linux.vnet.ibm.com> X-Mailer: git-send-email 2.1.0 In-Reply-To: <1463725945-12916-1-git-send-email-gwshan@linux.vnet.ibm.com> References: <1463725945-12916-1-git-send-email-gwshan@linux.vnet.ibm.com> X-TM-AS-MML: disable X-Content-Scanned: Fidelis XPS MAILER x-cbid: 16052006-1618-0000-0000-000045E2C962 X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused Subject: [Skiboot] [PATCH v11 16/23] hw/npu: Support PHB slot X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair@popple.id.au MIME-Version: 1.0 Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" This creates PCI slot before the PHB is registered. Nothing has been done in the PCI slot operations except to keep the PCI probe code going. Signed-off-by: Gavin Shan Reviewed-by: Russell Currey --- hw/npu.c | 57 ++++++++++++++++++++++++++++++++++++++++++--------------- 1 file changed, 42 insertions(+), 15 deletions(-) diff --git a/hw/npu.c b/hw/npu.c index 52ac4ab..fd0ed0a 100644 --- a/hw/npu.c +++ b/hw/npu.c @@ -18,6 +18,7 @@ #include #include #include +#include #include #include #include @@ -972,27 +973,29 @@ static int64_t npu_set_pe(struct phb *phb, return OPAL_SUCCESS; } -static int64_t npu_link_state(struct phb *phb __unused) +static int64_t npu_get_link_state(struct pci_slot *slot __unused, uint8_t *val) { /* As we're emulating all PCI stuff, the link bandwidth * isn't big deal anyway. */ - return OPAL_SHPC_LINK_UP_x1; + *val = OPAL_SHPC_LINK_UP_x1; + return OPAL_SUCCESS; } -static int64_t npu_power_state(struct phb *phb __unused) +static int64_t npu_get_power_state(struct pci_slot *slot __unused, uint8_t *val) { - return OPAL_SHPC_POWER_ON; + *val = PCI_SLOT_POWER_ON; + return OPAL_SUCCESS; } -static int64_t npu_hreset(struct phb *phb __unused) +static int64_t npu_hreset(struct pci_slot *slot __unused) { prlog(PR_DEBUG, "NPU: driver should call reset procedure here\n"); return OPAL_SUCCESS; } -static int64_t npu_freset(struct phb *phb __unused) +static int64_t npu_freset(struct pci_slot *slot __unused) { /* FIXME: PHB fundamental reset, which need to be * figured out later. It's used by EEH recovery @@ -1001,6 +1004,33 @@ static int64_t npu_freset(struct phb *phb __unused) return OPAL_SUCCESS; } +static struct pci_slot *npu_slot_create(struct phb *phb) +{ + struct pci_slot *slot; + + slot = pci_slot_alloc(phb, NULL); + if (!slot) + return slot; + + /* Elementary functions */ + slot->ops.get_presence_state = NULL; + slot->ops.get_link_state = npu_get_link_state; + slot->ops.get_power_state = npu_get_power_state; + slot->ops.get_attention_state = NULL; + slot->ops.get_latch_state = NULL; + slot->ops.set_power_state = NULL; + slot->ops.set_attention_state = NULL; + + slot->ops.prepare_link_change = NULL; + slot->ops.poll_link = NULL; + slot->ops.hreset = npu_hreset; + slot->ops.freset = npu_freset; + slot->ops.pfreset = NULL; + slot->ops.creset = NULL; + + return slot; +} + static int64_t npu_freeze_status(struct phb *phb, uint64_t pe_number __unused, uint8_t *freeze_state, @@ -1106,7 +1136,6 @@ static const struct phb_ops npu_ops = { .get_info = NULL, .device_init = NULL, .phb_final_fixup = npu_phb_final_fixup, - .presence_detect = NULL, .ioda_reset = npu_ioda_reset, .papr_errinjct_reset = NULL, .pci_reinit = NULL, @@ -1121,14 +1150,6 @@ static const struct phb_ops npu_ops = { .get_msi_64 = NULL, .set_pe = npu_set_pe, .set_peltv = NULL, - .link_state = npu_link_state, - .power_state = npu_power_state, - .slot_power_off = NULL, - .slot_power_on = NULL, - .hot_reset = npu_hreset, - .fundamental_reset = npu_freset, - .complete_reset = NULL, - .poll = NULL, .eeh_freeze_status = npu_freeze_status, .eeh_freeze_clear = NULL, .eeh_freeze_set = NULL, @@ -1749,6 +1770,7 @@ static void npu_create_phb(struct dt_node *dn) { const struct dt_property *prop; struct npu *p; + struct pci_slot *slot; uint32_t links; void *pmem; @@ -1793,6 +1815,11 @@ static void npu_create_phb(struct dt_node *dn) /* Populate extra properties */ npu_add_phb_properties(p); + /* Create PHB slot */ + slot = npu_slot_create(&p->phb); + if (!slot) + prlog(PR_ERR, "NPU: Cannot create PHB slot\n"); + /* Register PHB */ pci_register_phb(&p->phb, OPAL_DYNAMIC_PHB_ID);