From patchwork Mon Jan 18 05:59:40 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Russell Currey X-Patchwork-Id: 569442 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [103.22.144.68]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id C8D7514031D for ; Mon, 18 Jan 2016 17:00:07 +1100 (AEDT) Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 8C46F1A0CA4 for ; Mon, 18 Jan 2016 17:00:07 +1100 (AEDT) X-Original-To: skiboot@lists.ozlabs.org Delivered-To: skiboot@lists.ozlabs.org Received: from russell.cc (russell.cc [IPv6:2404:9400:2:0:216:3eff:fee0:3370]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id CFDBF1A003F for ; Mon, 18 Jan 2016 16:59:57 +1100 (AEDT) Received: from snap.ozlabs.ibm.com (static-82-10.transact.net.au [122.99.82.10]) by russell.cc (OpenSMTPD) with ESMTPSA id 43fc5d74 TLS version=TLSv1/SSLv3 cipher=ECDHE-RSA-AES128-SHA256 bits=128 verify=NO; Mon, 18 Jan 2016 05:59:51 +0000 (UTC) From: Russell Currey To: skiboot@lists.ozlabs.org Date: Mon, 18 Jan 2016 16:59:40 +1100 Message-Id: <1453096782-8398-2-git-send-email-ruscur@russell.cc> X-Mailer: git-send-email 2.7.0 In-Reply-To: <1453096782-8398-1-git-send-email-ruscur@russell.cc> References: <1453096782-8398-1-git-send-email-ruscur@russell.cc> Subject: [Skiboot] [PATCH V2 2/4] nvlink: Add fence mode emulation for NPUs X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" As NPUs are emulated PCI devices, they do not get physically fenced as real PCI devices do. As such, when the device is in a state that it should be fenced, we need to emulate this behaviour by returning all 1s in config space reads. This will be utilised by error injection in subsequent patches. Signed-off-by: Russell Currey Acked-By: Alistair Popple --- V2: Clarify fence comment and move freeze status change to this patch --- hw/npu.c | 15 +++++++++++++-- include/npu.h | 1 + 2 files changed, 14 insertions(+), 2 deletions(-) diff --git a/hw/npu.c b/hw/npu.c index 3a06c04..3c2c0b8 100644 --- a/hw/npu.c +++ b/hw/npu.c @@ -390,6 +390,10 @@ static int64_t _npu_dev_cfg_read(struct phb *phb, uint32_t bdfn, /* Data returned upon errors */ *data = 0xffffffff; + /* If fenced, we want to return all 1s, so we're done. */ + if (p->fenced) + return OPAL_SUCCESS; + /* Retrieve NPU device */ dev = npu_dev_cfg_check(p, bdfn, offset, size); if (!dev) @@ -996,7 +1000,7 @@ static int64_t npu_freset(struct phb *phb __unused) return OPAL_SUCCESS; } -static int64_t npu_freeze_status(struct phb *phb __unused, +static int64_t npu_freeze_status(struct phb *phb, uint64_t pe_number __unused, uint8_t *freeze_state, uint16_t *pci_error_type __unused, @@ -1008,7 +1012,11 @@ static int64_t npu_freeze_status(struct phb *phb __unused, * introduce another PHB callback to translate it. For now, * it keeps the skiboot PCI enumeration going. */ - *freeze_state = OPAL_EEH_STOPPED_NOT_FROZEN; + struct npu *p = phb_to_npu(phb); + if (p->fenced) + *freeze_state = OPAL_EEH_STOPPED_MMIO_DMA_FREEZE; + else + *freeze_state = OPAL_EEH_STOPPED_NOT_FROZEN; return OPAL_SUCCESS; } @@ -1680,6 +1688,9 @@ static void npu_create_phb(struct dt_node *dn) p->xscom_base = dt_prop_get_u32(dn, "ibm,xscom-base"); p->total_devices = links; + /* TODO: When hardware fences are implemented, detect them here */ + p->fenced = false; + /* This is the AT base */ p->at_xscom = p->xscom_base + NPU_AT_SCOM_OFFSET; p->at_regs = (void *)dt_get_address(dn, 0, NULL); diff --git a/include/npu.h b/include/npu.h index 795b704..5d5135b 100644 --- a/include/npu.h +++ b/include/npu.h @@ -167,6 +167,7 @@ struct npu { uint64_t tve_cache[NPU_NUM_OF_PES]; bool tx_zcal_complete[2]; + bool fenced; struct phb phb; };