From patchwork Thu Jan 7 03:36:31 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Russell Currey X-Patchwork-Id: 564162 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 902BB1402E2 for ; Thu, 7 Jan 2016 14:44:26 +1100 (AEDT) Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 735EA1A0B02 for ; Thu, 7 Jan 2016 14:44:26 +1100 (AEDT) X-Original-To: skiboot@lists.ozlabs.org Delivered-To: skiboot@lists.ozlabs.org Received: from russell.cc (russell.cc [IPv6:2404:9400:2:0:216:3eff:fee0:3370]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 045AF1A0228 for ; Thu, 7 Jan 2016 14:44:22 +1100 (AEDT) Received: from snap.ozlabs.ibm.com (static-82-10.transact.net.au [122.99.82.10]) by russell.cc (OpenSMTPD) with ESMTPSA id 04b16a66 TLS version=TLSv1/SSLv3 cipher=ECDHE-RSA-AES128-SHA256 bits=128 verify=NO; Thu, 7 Jan 2016 03:37:40 +0000 (UTC) From: Russell Currey To: skiboot@lists.ozlabs.org Date: Thu, 7 Jan 2016 14:36:31 +1100 Message-Id: <1452137792-24062-4-git-send-email-ruscur@russell.cc> X-Mailer: git-send-email 2.6.4 In-Reply-To: <1452137792-24062-1-git-send-email-ruscur@russell.cc> References: <1452137792-24062-1-git-send-email-ruscur@russell.cc> Subject: [Skiboot] [PATCH 4/5] nvlink: Add freeze and fence error injection X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair@popple.id.au MIME-Version: 1.0 Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" Enable NPU freeze and fence injection through debugfs. For example, if a NPU is PCI bus 8, a freeze on PE 0 can be injected with: echo 0:0:0:0:0 >> /sys/kernel/debug/powerpc/PCI0008/err_injct or a fence on PE 2 on PCI bus 9 with: echo 2:1:0:0:0 >> /sys/kernel/debug/powerpc/PCI0009/err_injct These will cause the appropriate EEH event to occur upon a DMA to the NVLink. Signed-off-by: Russell Currey --- hw/npu.c | 31 ++++++++++++++++++++++++++++++- 1 file changed, 30 insertions(+), 1 deletion(-) diff --git a/hw/npu.c b/hw/npu.c index 9440f17..ba61d2d 100644 --- a/hw/npu.c +++ b/hw/npu.c @@ -1016,6 +1016,35 @@ static int64_t npu_freeze_status(struct phb *phb __unused, return OPAL_SUCCESS; } +/* Sets the NPU to trigger an error when a DMA occurs */ +static int64_t npu_err_inject(struct phb *phb, uint32_t pe_no, + uint32_t type, uint32_t func __unused, + uint64_t addr __unused, uint64_t mask __unused) +{ + struct npu *p = phb_to_npu(phb); + struct npu_dev *dev; + + if (pe_no > NPU_NUM_OF_PES) { + prlog(PR_ERR, "NPU: error injection failed, bad PE given\n"); + return OPAL_SUCCESS; + } + + dev = &p->devices[pe_no]; + + /* TODO: extend this to conform to OPAL injection standards */ + if (type > 1) { + prlog(PR_ERR, "NPU: invalid error injection type\n"); + } else if (type == 1) { + /* Emulate fence mode. */ + p->fenced = true; + } else { + /* Cause a freeze with an invalid MMIO write. */ + in_be64((void *)dev->bar.base); + } + + return OPAL_SUCCESS; +} + static const struct phb_ops npu_ops = { .lock = npu_lock, .unlock = npu_unlock, @@ -1055,7 +1084,7 @@ static const struct phb_ops npu_ops = { .eeh_freeze_clear = NULL, .eeh_freeze_set = NULL, .next_error = NULL, - .err_inject = NULL, + .err_inject = npu_err_inject, .get_diag_data = NULL, .get_diag_data2 = NULL, .set_capi_mode = NULL,