From patchwork Thu Jan 7 03:36:28 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Russell Currey X-Patchwork-Id: 564159 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 75CD61402E2 for ; Thu, 7 Jan 2016 14:37:48 +1100 (AEDT) Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 346F81A0B02 for ; Thu, 7 Jan 2016 14:37:48 +1100 (AEDT) X-Original-To: skiboot@lists.ozlabs.org Delivered-To: skiboot@lists.ozlabs.org Received: from russell.cc (russell.cc [IPv6:2404:9400:2:0:216:3eff:fee0:3370]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 6C2381A0228 for ; Thu, 7 Jan 2016 14:37:44 +1100 (AEDT) Received: from snap.ozlabs.ibm.com (static-82-10.transact.net.au [122.99.82.10]) by russell.cc (OpenSMTPD) with ESMTPSA id eb548548 TLS version=TLSv1/SSLv3 cipher=ECDHE-RSA-AES128-SHA256 bits=128 verify=NO; Thu, 7 Jan 2016 03:37:40 +0000 (UTC) From: Russell Currey To: skiboot@lists.ozlabs.org Date: Thu, 7 Jan 2016 14:36:28 +1100 Message-Id: <1452137792-24062-1-git-send-email-ruscur@russell.cc> X-Mailer: git-send-email 2.6.4 Subject: [Skiboot] [PATCH 1/5] nvlink: Use SCOMs instead of MMIO in reset procedure X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair@popple.id.au MIME-Version: 1.0 Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" EEH in the kernel shuts down MMIO BARs as part of freeze recovery. This can cause the reset procedure, which you probably want to work during a freeze, to fail because it can't do operations with MMIO. Refactor the MMIO operations to use SCOM instead. Signed-off-by: Russell Currey Acked-By: Alistair Popple --- hw/npu-hw-procedures.c | 16 +++++++--------- 1 file changed, 7 insertions(+), 9 deletions(-) diff --git a/hw/npu-hw-procedures.c b/hw/npu-hw-procedures.c index 118ed6d..24f3b2c 100644 --- a/hw/npu-hw-procedures.c +++ b/hw/npu-hw-procedures.c @@ -132,13 +132,12 @@ DEFINE_PROCEDURE(nop); * incorporates AT reset. */ static uint32_t reset_npu_dl(struct npu_dev *npu_dev) { - void *ntl_base = (void *) npu_dev->bar.base; uint64_t val; /* Assert NPU reset */ - val = in_be64(ntl_base + NTL_CONTROL); + xscom_read(npu_dev->npu->chip_id, npu_dev->xscom + NX_NTL_CONTROL, &val); val |= NTL_CONTROL_RESET; - out_be64(ntl_base + NTL_CONTROL, val); + xscom_write(npu_dev->npu->chip_id, npu_dev->xscom + NX_NTL_CONTROL, val); /* Put the Nvidia logic in reset */ dl_write(npu_dev, NDL_CONTROL, 0xe8000000); @@ -148,14 +147,13 @@ static uint32_t reset_npu_dl(struct npu_dev *npu_dev) /* Release NPU from reset */ val &= ~NTL_CONTROL_RESET; - out_be64(ntl_base + NTL_CONTROL, val); + xscom_write(npu_dev->npu->chip_id, npu_dev->xscom + NX_NTL_CONTROL, val); /* Setup up TL credits */ - out_be64(ntl_base + TL_CMD_CR, PPC_BIT(0)); - out_be64(ntl_base + TL_CMD_D_CR, PPC_BIT(0)); - out_be64(ntl_base + TL_RSP_CR, PPC_BIT(15)); - out_be64(ntl_base + TL_RSP_D_CR, PPC_BIT(15)); - + xscom_write(npu_dev->npu->chip_id, npu_dev->xscom + NX_TL_CMD_CR, PPC_BIT(0)); + xscom_write(npu_dev->npu->chip_id, npu_dev->xscom + NX_TL_CMD_D_CR, PPC_BIT(0)); + xscom_write(npu_dev->npu->chip_id, npu_dev->xscom + NX_TL_RSP_CR, PPC_BIT(15)); + xscom_write(npu_dev->npu->chip_id, npu_dev->xscom + NX_TL_RSP_D_CR, PPC_BIT(15)); return PROCEDURE_COMPLETE; } DEFINE_PROCEDURE(reset_npu_dl);