From patchwork Wed Nov 18 00:34:04 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Benjamin Herrenschmidt X-Patchwork-Id: 545823 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 1526014144B for ; Wed, 18 Nov 2015 11:34:13 +1100 (AEDT) Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id ED56E1A074A for ; Wed, 18 Nov 2015 11:34:12 +1100 (AEDT) X-Original-To: skiboot@lists.ozlabs.org Delivered-To: skiboot@lists.ozlabs.org Received: from gate.crashing.org (gate.crashing.org [63.228.1.57]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 5685B1A06D5 for ; Wed, 18 Nov 2015 11:34:09 +1100 (AEDT) Received: from localhost.localdomain (localhost.localdomain [127.0.0.1]) by gate.crashing.org (8.14.1/8.13.8) with ESMTP id tAI0Y4ap027979 for ; Tue, 17 Nov 2015 18:34:05 -0600 Message-ID: <1447806844.3729.57.camel@kernel.crashing.org> From: Benjamin Herrenschmidt To: skiboot list Date: Wed, 18 Nov 2015 11:34:04 +1100 X-Mailer: Evolution 3.18.1 (3.18.1-1.fc23) Mime-Version: 1.0 Subject: [Skiboot] [PATCH] hw/phb3: Flush cache line after updating P/Q bits X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" When doing an MSI EOI, we update the P and Q bits in the IVE. That causes the corresponding cache line to be dirty in the L3 which will cause a subsequent update by the PHB (upon recieving the next MSI) to get a few retries until it gets flushed. We can improve the situation (and thus performance) by doing a dcbf instruction to force a flush of the update we do in SW. Signed-off-by: Benjamin Herrenschmidt diff --git a/hw/phb3.c b/hw/phb3.c index 36e8c58..220740a 100644 --- a/hw/phb3.c +++ b/hw/phb3.c @@ -1045,7 +1045,7 @@ static int64_t phb3_map_pe_dma_window_real(struct phb *phb,   return OPAL_SUCCESS;  }   -static void phb3_pci_msi_check_q(struct phb3 *p, uint32_t ive_num) +static bool phb3_pci_msi_check_q(struct phb3 *p, uint32_t ive_num)  {   uint64_t ive, ivc, ffi, state;   uint8_t *q_byte; @@ -1067,7 +1067,7 @@ static void phb3_pci_msi_check_q(struct phb3 *p, uint32_t ive_num)     /* Q still not set, bail out */   if (!(*q_byte & 0x1)) - return; + return false;   }     /* Lock FFI and send interrupt */ @@ -1076,7 +1076,7 @@ static void phb3_pci_msi_check_q(struct phb3 *p, uint32_t ive_num)   if (!state)   break;   if (state == ~0ULL) /* PHB Fenced */ - return; + return false;   }     /* Clear Q bit and update IVC */ @@ -1092,6 +1092,16 @@ static void phb3_pci_msi_check_q(struct phb3 *p, uint32_t ive_num)    */   ffi = SETFIELD(PHB_FFI_REQUEST_ISN, 0ul, ive_num) | PHB_FFI_LOCK_CLEAR;   out_be64(p->regs + PHB_FFI_REQUEST, ffi); + + return true; +} + +static void phb3_pci_msi_flush_ive(struct phb3 *p, uint32_t ive_num) +{ + asm volatile("dcbf %0,%1" +      : +      : "b" (p->tbl_ivt), "r" (ive_num * IVT_TABLE_STRIDE * 8) +      : "memory");  }    static int64_t phb3_pci_msi_eoi(struct phb *phb, @@ -1127,6 +1137,8 @@ static int64_t phb3_pci_msi_eoi(struct phb *phb,   /* Handle Q bit */   phb3_pci_msi_check_q(p, ive_num);   + phb3_pci_msi_flush_ive(p, ive_num); +   return OPAL_SUCCESS;  }   @@ -1637,8 +1649,10 @@ static int64_t phb3_msi_set_xive(void *data,    * The OS should make sure the interrupt handler has    * been installed already.    */ - if (prio != 0xff) - phb3_pci_msi_check_q(p, ive_num); + if (prio != 0xff) { + if (phb3_pci_msi_check_q(p, ive_num)) + phb3_pci_msi_flush_ive(p, ive_num); + }     return OPAL_SUCCESS;  }