From patchwork Fri Sep 11 04:36:34 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gavin Shan X-Patchwork-Id: 516544 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 7021614030C for ; Fri, 11 Sep 2015 14:37:41 +1000 (AEST) Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 5ABD21A2B20 for ; Fri, 11 Sep 2015 14:37:41 +1000 (AEST) X-Original-To: skiboot@lists.ozlabs.org Delivered-To: skiboot@lists.ozlabs.org Received: from e23smtp08.au.ibm.com (e23smtp08.au.ibm.com [202.81.31.141]) (using TLSv1 with cipher CAMELLIA256-SHA (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 12D841A1F40 for ; Fri, 11 Sep 2015 14:37:37 +1000 (AEST) Received: from /spool/local by e23smtp08.au.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! 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Violators will be prosecuted; Fri, 11 Sep 2015 14:37:32 +1000 X-Helo: d23dlp02.au.ibm.com X-MailFrom: gwshan@linux.vnet.ibm.com X-RcptTo: skiboot@lists.ozlabs.org Received: from d23relay09.au.ibm.com (d23relay09.au.ibm.com [9.185.63.181]) by d23dlp02.au.ibm.com (Postfix) with ESMTP id 71E392BB0051 for ; Fri, 11 Sep 2015 14:37:32 +1000 (EST) Received: from d23av03.au.ibm.com (d23av03.au.ibm.com [9.190.234.97]) by d23relay09.au.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id t8B4bNiZ60293374 for ; Fri, 11 Sep 2015 14:37:32 +1000 Received: from d23av03.au.ibm.com (localhost [127.0.0.1]) by d23av03.au.ibm.com (8.14.4/8.14.4/NCO v10.0 AVout) with ESMTP id t8B4axO3026254 for ; Fri, 11 Sep 2015 14:36:59 +1000 Received: from ozlabs.au.ibm.com (ozlabs.au.ibm.com [9.192.253.14]) by d23av03.au.ibm.com (8.14.4/8.14.4/NCO v10.0 AVin) with ESMTP id t8B4axRS025898; Fri, 11 Sep 2015 14:36:59 +1000 Received: from bran.ozlabs.ibm.com (haven.au.ibm.com [9.192.254.114]) by ozlabs.au.ibm.com (Postfix) with ESMTP id 4DB3DA01C7; Fri, 11 Sep 2015 14:36:35 +1000 (AEST) Received: from gwshan (shangw.ozlabs.ibm.com [10.61.2.199]) by bran.ozlabs.ibm.com (Postfix) with ESMTP id 3F957E450B; Fri, 11 Sep 2015 14:36:35 +1000 (AEST) Received: by gwshan (Postfix, from userid 1000) id 29B70941E9A; Fri, 11 Sep 2015 14:36:35 +1000 (AEST) From: Gavin Shan To: skiboot@lists.ozlabs.org Date: Fri, 11 Sep 2015 14:36:34 +1000 Message-Id: <1441946194-22437-1-git-send-email-gwshan@linux.vnet.ibm.com> X-Mailer: git-send-email 2.1.0 X-TM-AS-MML: disable X-Content-Scanned: Fidelis XPS MAILER x-cbid: 15091104-0029-0000-0000-00000226E32E Subject: [Skiboot] [PATCH] PCI: Clear error bits after changing MPS X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" Chaning MPS on PCI upstream bridge might cause error bits set on downstream endpoints when system boots into Linux as below case shows: host# lspci -vvs 0001:06:00.0 0001:06:00.0 Ethernet controller: Broadcom Corporation \ NetXtreme II BCM57810 10 Gigabit Ethernet (rev 10) : DevSta: CorrErr+ UncorrErr- FatalErr- UnsuppReq+ AuxPwr- TransPend- : CESta: RxErr- BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr+ This clears those error bits in AER and PCIe capability after MPS is changed. With the patch applied, no more error bits are seen. Reported-by: John Walthour Signed-off-by: Gavin Shan --- core/pci.c | 22 +++++++++++++++++++--- 1 file changed, 19 insertions(+), 3 deletions(-) diff --git a/core/pci.c b/core/pci.c index 26ed48c..6cfb3cb 100644 --- a/core/pci.c +++ b/core/pci.c @@ -609,20 +609,23 @@ static int pci_configure_mps(struct phb *phb, struct pci_device *pd, void *userdata __unused) { - uint32_t ecap, mps; + uint32_t ecap, aercap, mps; uint16_t val; assert(phb); assert(pd); - mps = phb->mps; /* If the MPS isn't acceptable one, bail immediately */ + mps = phb->mps; if (mps < 128 || mps > 4096) return 1; + /* Retrieve PCIe and AER capability */ + ecap = pci_cap(pd, PCI_CFG_CAP_ID_EXP, false); + aercap = pci_cap(pd, PCIECAP_ID_AER, true); + /* PCIe device always has MPS capacity */ if (pd->mps) { - ecap = pci_cap(pd, PCI_CFG_CAP_ID_EXP, false); mps = ilog2(mps) - 7; pci_cfg_read16(phb, pd->bdfn, ecap + PCICAP_EXP_DEVCTL, &val); @@ -630,6 +633,19 @@ static int pci_configure_mps(struct phb *phb, pci_cfg_write16(phb, pd->bdfn, ecap + PCICAP_EXP_DEVCTL, val); } + /* Changing MPS on upstream PCI bridge might cause some error + * bits in PCIe and AER capability. To clear them to avoid + * confusion. + */ + if (aercap) { + pci_cfg_write32(phb, pd->bdfn, aercap + PCIECAP_AER_UE_STATUS, + 0xffffffff); + pci_cfg_write32(phb, pd->bdfn, aercap + PCIECAP_AER_CE_STATUS, + 0xffffffff); + } + if (ecap) + pci_cfg_write16(phb, pd->bdfn, ecap + PCICAP_EXP_DEVSTAT, 0xf); + return 0; }