From patchwork Mon Jun 29 00:44:21 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gavin Shan X-Patchwork-Id: 489191 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 79E7C140332 for ; Mon, 29 Jun 2015 10:45:33 +1000 (AEST) Received: from ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 664D91A0FEC for ; Mon, 29 Jun 2015 10:45:33 +1000 (AEST) X-Original-To: skiboot@lists.ozlabs.org Delivered-To: skiboot@lists.ozlabs.org Received: from e23smtp09.au.ibm.com (e23smtp09.au.ibm.com [202.81.31.142]) (using TLSv1 with cipher CAMELLIA256-SHA (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 9DEAF1A02D8 for ; Mon, 29 Jun 2015 10:45:25 +1000 (AEST) Received: from /spool/local by e23smtp09.au.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! 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Violators will be prosecuted; Mon, 29 Jun 2015 10:45:22 +1000 X-Helo: d23dlp03.au.ibm.com X-MailFrom: gwshan@linux.vnet.ibm.com X-RcptTo: skiboot@lists.ozlabs.org Received: from d23relay06.au.ibm.com (d23relay06.au.ibm.com [9.185.63.219]) by d23dlp03.au.ibm.com (Postfix) with ESMTP id 2329A3578048 for ; Mon, 29 Jun 2015 10:45:22 +1000 (EST) Received: from d23av01.au.ibm.com (d23av01.au.ibm.com [9.190.234.96]) by d23relay06.au.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id t5T0jCAQ65667102 for ; Mon, 29 Jun 2015 10:45:21 +1000 Received: from d23av01.au.ibm.com (localhost [127.0.0.1]) by d23av01.au.ibm.com (8.14.4/8.14.4/NCO v10.0 AVout) with ESMTP id t5T0inCp023688 for ; Mon, 29 Jun 2015 10:44:49 +1000 Received: from ozlabs.au.ibm.com (ozlabs.au.ibm.com [9.192.253.14]) by d23av01.au.ibm.com (8.14.4/8.14.4/NCO v10.0 AVin) with ESMTP id t5T0imYx023255; Mon, 29 Jun 2015 10:44:48 +1000 Received: from bran.ozlabs.ibm.com (unknown [9.192.254.114]) by ozlabs.au.ibm.com (Postfix) with ESMTP id 1EBE7A0321; Mon, 29 Jun 2015 10:44:24 +1000 (AEST) Received: from gwshan (shangw.ozlabs.ibm.com [10.61.2.199]) by bran.ozlabs.ibm.com (Postfix) with ESMTP id 14729E38CF; Mon, 29 Jun 2015 10:44:24 +1000 (AEST) Received: by gwshan (Postfix, from userid 1000) id 0EF6F941903; Mon, 29 Jun 2015 10:44:24 +1000 (AEST) From: Gavin Shan To: skiboot@lists.ozlabs.org Date: Mon, 29 Jun 2015 10:44:21 +1000 Message-Id: <1435538662-8675-2-git-send-email-gwshan@linux.vnet.ibm.com> X-Mailer: git-send-email 2.1.0 In-Reply-To: <1435538662-8675-1-git-send-email-gwshan@linux.vnet.ibm.com> References: <1435538662-8675-1-git-send-email-gwshan@linux.vnet.ibm.com> X-TM-AS-MML: disable X-Content-Scanned: Fidelis XPS MAILER x-cbid: 15062900-0033-0000-0000-000001B1DB0E Subject: [Skiboot] [PATCH 1/2] hw/phb3: Support config error injection to VF PE X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" Before the SRIOV is enabled, the only supported PE type is PCI bus dependent PE when doing error injection via PCI config space. That means the device/function number are ignored when writing to PAPR error injection address/mask registers (0x2b8 and 0x2c0) to inject PCI config access caused errors. If user intends to inject error to one VF, which is binding with individual PE, all VFs hooked to same PCI bus might receive errors wrongly. The patch fixes above issue by writing correct PCI config address to the registers according to the PE type: bus dependent or PCI device dependent PE. Signed-off-by: Gavin Shan --- hw/phb3.c | 45 ++++++++++++++++++++++++++++++--------------- include/phb3-regs.h | 1 + 2 files changed, 31 insertions(+), 15 deletions(-) diff --git a/hw/phb3.c b/hw/phb3.c index 9b4444c..9d52c84 100644 --- a/hw/phb3.c +++ b/hw/phb3.c @@ -2891,25 +2891,42 @@ static int64_t phb3_err_inject_cfg(struct phb3 *p, uint32_t pe_no, { uint64_t a, m, prefer; uint64_t ctrl = PHB_PAPR_ERR_INJ_CTL_CFG; - int bus_no, bdfn; + int bdfn; + bool is_bus_pe; a = 0xffffull; prefer = 0xffffull; + m = PHB_PAPR_ERR_INJ_MASK_CFG_ALL; for (bdfn = 0; bdfn < RTT_TABLE_ENTRIES; bdfn++) { if (p->rte_cache[bdfn] != pe_no) continue; - /* Select minimal bus number as PE - * primary bus number - */ - bus_no = (bdfn >> 8); - if (prefer == 0xffffull) - prefer = SETFIELD(PHB_PAPR_ERR_INJ_MASK_CFG, 0x0ull, bus_no); + /* The PE can be associated with PCI bus or device */ + is_bus_pe = false; + if ((bdfn + 8) < RTT_TABLE_ENTRIES && + p->rte_cache[bdfn + 8] == pe_no) + is_bus_pe = true; + + /* Figure out the PCI config address */ + if (prefer == 0xffffull) { + if (is_bus_pe) { + m = PHB_PAPR_ERR_INJ_MASK_CFG; + prefer = SETFIELD(m, 0x0ull, (bdfn >> 8)); + } else { + m = PHB_PAPR_ERR_INJ_MASK_CFG_ALL; + prefer = SETFIELD(m, 0x0ull, bdfn); + } + } - /* Address should no greater than max bus - * number within PE - */ - if ((GETFIELD(PHB_PAPR_ERR_INJ_MASK_CFG, addr) == bus_no)) { + /* Check the input address is valid or not */ + if (!is_bus_pe && + GETFIELD(PHB_PAPR_ERR_INJ_MASK_CFG_ALL, addr) == bdfn) { + a = addr; + break; + } + + if (is_bus_pe && + GETFIELD(PHB_PAPR_ERR_INJ_MASK_CFG, addr) == (bdfn >> 8)) { a = addr; break; } @@ -2920,12 +2937,10 @@ static int64_t phb3_err_inject_cfg(struct phb3 *p, uint32_t pe_no, return OPAL_PARAMETER; /* Specified address is out of range */ - if (a == 0xffffull) { + if (a == 0xffffull) a = prefer; - m = PHB_PAPR_ERR_INJ_MASK_CFG; - } else { + else m = mask; - } return phb3_err_inject_finalize(p, a, m, ctrl, is_write); } diff --git a/include/phb3-regs.h b/include/phb3-regs.h index 632ed93..91f25f9 100644 --- a/include/phb3-regs.h +++ b/include/phb3-regs.h @@ -123,6 +123,7 @@ #define PHB_PAPR_ERR_INJ_ADDR_MMIO PPC_BITMASK(16,63) #define PHB_PAPR_ERR_INJ_MASK 0x2c0 #define PHB_PAPR_ERR_INJ_MASK_CFG PPC_BITMASK(4,11) +#define PHB_PAPR_ERR_INJ_MASK_CFG_ALL PPC_BITMASK(4,19) #define PHB_PAPR_ERR_INJ_MASK_MMIO PPC_BITMASK(16,63) #define PHB_ETU_ERR_SUMMARY 0x2c8