From patchwork Tue Jun 23 04:25:53 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Benjamin Herrenschmidt X-Patchwork-Id: 487505 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 642A8140157 for ; Tue, 23 Jun 2015 14:27:15 +1000 (AEST) Received: from ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 49DDB1A0FD9 for ; Tue, 23 Jun 2015 14:27:15 +1000 (AEST) X-Original-To: skiboot@lists.ozlabs.org Delivered-To: skiboot@lists.ozlabs.org Received: from gate.crashing.org (gate.crashing.org [63.228.1.57]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 5D0411A001E for ; Tue, 23 Jun 2015 14:26:35 +1000 (AEST) Received: from pasglop.ozlabs.ibm.com (localhost.localdomain [127.0.0.1]) by gate.crashing.org (8.14.1/8.13.8) with ESMTP id t5N4Q2mM029011; Mon, 22 Jun 2015 23:26:05 -0500 From: Benjamin Herrenschmidt To: skiboot@lists.ozlabs.org Date: Tue, 23 Jun 2015 14:25:53 +1000 Message-Id: <1435033560-9180-3-git-send-email-benh@kernel.crashing.org> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1435033560-9180-1-git-send-email-benh@kernel.crashing.org> References: <1435033560-9180-1-git-send-email-benh@kernel.crashing.org> Subject: [Skiboot] [PATCH 03/10] centaur: Add API to enable/disable the sensor cache X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" The i2c driver will need to use them to avoid conflicts between i2c accesses initiated by the host and by the sensor cache. Signed-off-by: Benjamin Herrenschmidt --- hw/centaur.c | 59 +++++++++++++++++++++++++++++++++++++++++++++++++++++++ include/centaur.h | 4 ++++ 2 files changed, 63 insertions(+) diff --git a/hw/centaur.c b/hw/centaur.c index 6504e92..24d2836 100644 --- a/hw/centaur.c +++ b/hw/centaur.c @@ -21,6 +21,7 @@ #include #include #include +#include /* * Centaur chip IDs are using the XSCOM "partID" encoding @@ -52,6 +53,12 @@ #define FSI_STATUS_ABORT 0x00100000 #define FSI_STATUS_ERRORS 0x00007000 +/* Some Centaur XSCOMs we care about */ +#define SCAC_CONFIG_REG 0x020115ce +#define SCAC_CONFIG_SET 0x020115cf +#define SCAC_CONFIG_CLR 0x020115d0 +#define SCAC_ENABLE_MSK PPC_BIT(0) + static int64_t centaur_fsiscom_complete(struct centaur_chip *centaur) { int64_t rc; @@ -296,6 +303,58 @@ static bool centaur_add(uint32_t part_id, uint32_t mchip, uint32_t meng, return true; } +/* Returns how long to wait for logic to stop in TB ticks or a negative + * value on error + */ +int64_t centaur_disable_sensor_cache(uint32_t part_id) +{ + struct centaur_chip *centaur = get_centaur(part_id); + int64_t rc = 0; + uint64_t ctrl; + + if (!centaur) + return false; + + lock(¢aur->lock); + centaur->scache_disable_count++; + if (centaur->scache_disable_count == 1) { + centaur->scache_was_enabled = false; + rc = centaur_fsiscom_read(centaur, SCAC_CONFIG_REG, &ctrl); + if (rc) + goto bail; + centaur->scache_was_enabled = !!(ctrl & SCAC_ENABLE_MSK); + rc = centaur_fsiscom_write(centaur, SCAC_CONFIG_CLR, SCAC_ENABLE_MSK); + if (rc) + goto bail; + rc = msecs_to_tb(30); + } + bail: + unlock(¢aur->lock); + return rc; +} + +int64_t centaur_enable_sensor_cache(uint32_t part_id) +{ + struct centaur_chip *centaur = get_centaur(part_id); + int64_t rc = 0; + + if (!centaur) + return false; + + lock(¢aur->lock); + if (centaur->scache_disable_count == 0) { + prerror("CENTAUR: Cache count going negative !\n"); + backtrace(); + goto bail; + } + centaur->scache_disable_count--; + if (centaur->scache_disable_count == 0 && centaur->scache_was_enabled) + rc = centaur_fsiscom_write(centaur, SCAC_CONFIG_SET, SCAC_ENABLE_MSK); + bail: + unlock(¢aur->lock); + return rc; +} + void centaur_init(void) { struct dt_node *cn; diff --git a/include/centaur.h b/include/centaur.h index 457afd7..5412475 100644 --- a/include/centaur.h +++ b/include/centaur.h @@ -28,9 +28,13 @@ struct centaur_chip { uint32_t fsi_master_chip_id; uint32_t fsi_master_port; uint32_t fsi_master_engine; + uint32_t scache_disable_count; + bool scache_was_enabled; struct lock lock; }; +extern int64_t centaur_disable_sensor_cache(uint32_t part_id); +extern int64_t centaur_enable_sensor_cache(uint32_t part_id); extern int64_t centaur_xscom_read(uint32_t id, uint64_t pcb_addr, uint64_t *val) __warn_unused_result; extern int64_t centaur_xscom_write(uint32_t id, uint64_t pcb_addr, uint64_t val) __warn_unused_result;