From patchwork Thu Jun 18 05:30:33 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Benjamin Herrenschmidt X-Patchwork-Id: 486065 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 7DA791401E7 for ; Thu, 18 Jun 2015 15:30:43 +1000 (AEST) Received: from ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 655441A0E52 for ; Thu, 18 Jun 2015 15:30:43 +1000 (AEST) X-Original-To: skiboot@lists.ozlabs.org Delivered-To: skiboot@lists.ozlabs.org Received: from gate.crashing.org (gate.crashing.org [63.228.1.57]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id DB4F01A0E3C for ; Thu, 18 Jun 2015 15:30:37 +1000 (AEST) Received: from localhost (localhost.localdomain [127.0.0.1]) by gate.crashing.org (8.14.1/8.13.8) with ESMTP id t5I5UXOh028464 for ; Thu, 18 Jun 2015 00:30:34 -0500 Message-ID: <1434605433.3678.98.camel@kernel.crashing.org> From: Benjamin Herrenschmidt To: skiboot@lists.ozlabs.org Date: Thu, 18 Jun 2015 15:30:33 +1000 X-Mailer: Evolution 3.12.11-0ubuntu3 Mime-Version: 1.0 Subject: [Skiboot] [PATCH] Set proper value for RPR register X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" The value was provided by Dave Larson and is what pHyp uses Signed-off-by: Benjamin Herrenschmidt diff --git a/asm/head.S b/asm/head.S index fd6e3fb..6963188 100644 --- a/asm/head.S +++ b/asm/head.S @@ -707,6 +707,9 @@ init_shared_sprs: sync mtspr SPR_HMEER,%r3 isync + /* RPR (per-LPAR but let's treat it as replicated for now) */ + LOAD_IMM64(%r3,0x00000103070F1F3F) + mtspr SPR_RPR,%r3 9: blr .global init_replicated_sprs diff --git a/include/processor.h b/include/processor.h index c9e9d0e..e8f0c3c 100644 --- a/include/processor.h +++ b/include/processor.h @@ -52,6 +52,7 @@ #define SPR_SRR0 0x01a /* RW: Exception save/restore reg 0 */ #define SPR_SRR1 0x01b /* RW: Exception save/restore reg 1 */ #define SPR_CFAR 0x01c /* RW: Come From Address Register */ +#define SPR_RPR 0x0ba /* RW: Relative Priority Register */ #define SPR_TBRL 0x10c /* RO: Timebase low */ #define SPR_TBRU 0x10d /* RO: Timebase high */ #define SPR_SPRC 0x114 /* RW: Access to uArch SPRs (ex SCOMC) */